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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160064323A1

    公开(公告)日：2016-03-03

    申请号：US14835284

    申请日：2015-08-25

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hiroaki SEKIKAWA ,  Hidenori SATO ,  Yotaro GOTO ,  Takuya MARUYAMA ,  Masaaki SHINOHARA

    IPC: H01L23/528 ,  H01L27/146 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L27/14636 ,  H01L21/31051 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L22/30 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14603 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

    Abstract translation: 连接部分将铜基第一布线层与布置在第一扩散阻挡膜的上侧上的铜基第二布线层连接。 第一扩散阻挡膜包括在二维视图中形成在作为二维视图的局部区域的半导体电路区域中形成的第一开口区域和形成为与二维视图中的第一开口区域不同的开口区域的第二开口区域。 开口区域形成在与形成为允许连接部分穿过第一扩散阻挡膜的开口区域不同的区域中。 标记布线层设置在与第二布线层相同的层的正上方的第二开口区域的正上方。 第二扩散阻挡膜布置成与标记布线层的上表面接触。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190326434A1

    公开(公告)日：2019-10-24

    申请号：US16375634

    申请日：2019-04-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hiroaki SEKIKAWA ,  Takahiro MORI ,  Yuji ISHII

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L21/033 ,  H01L21/308 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

    Abstract: A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160372509A1

    公开(公告)日：2016-12-22

    申请号：US14910688

    申请日：2015-02-13

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hiroaki SEKIKAWA

    IPC: H01L27/146

    CPC classification number: H01L27/14636 ,  H01L21/82 ,  H01L23/522 ,  H01L27/14 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14687

    Abstract: A semiconductor device includes a plurality of wirings (WR11) which are formed in the same layer above a semiconductor substrate, and a plurality of wirings (WR12) which are formed in the same layer as that of the plurality of wirings (WR11). The plurality of wirings (WR11) are extended in an X axis direction and arranged at a pitch (PT11) in a Y axis direction intersecting with the X axis direction when seen in a plan view, and the plurality of wirings (WR12) are extended in the X axis direction and arranged at a pitch (PT12) in the Y axis direction when seen in a plan view. The plurality of wirings (WR11) are electrically connected to the plurality of wirings (WR12), and the pitch (PT11) is smaller than the pitch (PT12).

    Abstract translation: 半导体器件包括形成在半导体衬底上的相同层中的多个布线（WR11）和与多个布线（WR11）的层中形成的多个布线（WR12）。 多个布线（WR11）在俯视图中沿X轴方向延伸并且以与X轴方向交叉的Y轴方向的间距（PT11）配置，并且多根布线（WR12）被延伸 在俯视图中以X轴方向以Y轴方向以间距（PT12）配置。 多个布线（WR11）电连接到多个布线（WR12），并且间距（PT11）小于间距（PT12）。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190198453A1

    公开(公告)日：2019-06-27

    申请号：US16194005

    申请日：2018-11-16

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hiroaki SEKIKAWA

    IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78

    CPC classification number: H01L23/562 ,  H01L21/76224 ,  H01L21/78

    Abstract: It is prevented that reliability of a semiconductor device is reduced due to advancement of cracking or chipping within a substrate from a scribe region side to a circuit region side of a semiconductor chip. A dummy isolation part is formed from the upper surface to an intermediate depth of the substrate in a peripheral region that is a part of a scribe region adjacent to a seal ring region, and is not cut during dicing. The dummy isolation part having a DTI structure is disposed so as to surround the circuit region and the seal ring region.

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