公开(公告)号：US11233037B2

公开(公告)日：2022-01-25

申请号：US16492307

申请日：2018-04-18

Applicant: ROHM CO., LTD.

Inventor： Kenji Hayashi ,  Akihiro Suzaki ,  Masaaki Matsuo ,  Ryuta Watanabe ,  Makoto Ikenaga

IPC: H01L25/07 ,  H01L23/049 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373 ,  H01L23/00

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

公开(公告)号：US11302665B2

公开(公告)日：2022-04-12

申请号：US16676011

申请日：2019-11-06

Applicant: ROHM CO., LTD.

Inventor： Takukazu Otsuka ,  Seita Iwahashi ,  Maiko Hatano ,  Ryuta Watanabe ,  Katsuhiko Yoshihara

IPC: H01L23/495 ,  H01L23/00

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

公开(公告)号：US12191275B2

公开(公告)日：2025-01-07

申请号：US18496093

申请日：2023-10-27

Applicant: ROHM CO., LTD.

Inventor： Takukazu Otsuka ,  Seita Iwahashi ,  Maiko Hatano ,  Ryuta Watanabe ,  Katsuhiko Yoshihara

IPC: H01L23/00 ,  H01L23/495

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

公开(公告)号：US11848295B2

公开(公告)日：2023-12-19

申请号：US17685057

申请日：2022-03-02

Applicant: ROHM CO., LTD.

Inventor： Takukazu Otsuka ,  Seita Iwahashi ,  Maiko Hatano ,  Ryuta Watanabe ,  Katsuhiko Yoshihara

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/29 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/37 ,  H01L24/45 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L2224/32225 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/30101 ,  H01L2924/351

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

公开(公告)号：US11776936B2

公开(公告)日：2023-10-03

申请号：US17644452

申请日：2021-12-15

Applicant: ROHM CO., LTD.

Inventor： Kenji Hayashi ,  Akihiro Suzaki ,  Masaaki Matsuo ,  Ryuta Watanabe ,  Makoto Ikenaga

IPC: H01L25/07 ,  H01L23/049 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L23/049 ,  H01L23/296 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/564 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/40139 ,  H01L2224/40225 ,  H01L2224/48096 ,  H01L2224/48139 ,  H01L2224/48225 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/14252

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.