公开(公告)号：US20240290757A1

公开(公告)日：2024-08-29

申请号：US18174837

申请日：2023-02-27

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yusheng LIN

IPC分类号： H01L25/07 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/071 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/538 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/38 ,  H01L2224/40101 ,  H01L2224/40105 ,  H01L2224/40139 ,  H01L2224/40147 ,  H01L2224/4103 ,  H01L2224/4112 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8493

摘要： A transistor configured for higher power can be constructed using multiple transistor dies coupled in parallel. This approach of distributing power and heat over multiple transistor dies can allow each transistor die to be made smaller, which can be helpful in improving yield. This is especially true for emerging technologies, such as silicon carbide (SiC). Power modules for power conversion may require a plurality of these multi-die transistors in a package. A package that accommodates the numerous connections required for a multi-die power module is disclosed. The package utilizes a lead frame to provide a three-dimensional sandwich structure in which multiple dies are positioned between two direct bonded copper (DBC) substrates.

公开(公告)号：US12014974B2

公开(公告)日：2024-06-18

申请号：US17615206

申请日：2019-07-02

申请人： Mitsubishi Electric Corporation

发明人： Masakazu Tani

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/433 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L23/49575 ,  H01L21/565 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/40 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L2224/40139 ,  H01L2924/181

摘要： A manufacturing method for a power module capable of shortening a manufacturing time for a power module is obtained. The manufacturing method for a power module includes: a subassembly arranging step of placing a subassembly including a first electrode, a semiconductor device, and a second electrode on a heat sink via a joining material; and a transfer molding step of, after the subassembly arranging step, under a state in which the first electrode, the semiconductor device, and a second-electrode inner portion are arranged in a region surrounded by the heat sink and a molding die, injecting a thermoplastic resin into the region, wherein, in the transfer molding step, the subassembly is joined to the heat sink via the joining material with use of the resin.

公开(公告)号：US20240170441A1

公开(公告)日：2024-05-23

申请号：US18421658

申请日：2024-01-24

申请人： ROHM CO., LTD.

发明人： Kenji HAYASHI ,  Kohei TANIKAWA ,  Ryosuke FUKUDA

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07

CPC分类号： H01L24/40 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/29575 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40101 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/73263 ,  H01L2224/8383 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/35121

摘要： A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion. The semiconductor module further includes: a first conducting member connected to the first semiconductor elements and second conductive portion; and a second conducting member connected to the second semiconductor elements and second input terminal.

公开(公告)号：US20230402432A1

公开(公告)日：2023-12-14

申请号：US18455971

申请日：2023-08-25

申请人： ROHM CO., LTD.

发明人： Kenji HAYASHI ,  Akihiro SUZAKI ,  Masaaki MATSUO ,  Ryuta WATANABE ,  Makoto IKENAGA

IPC分类号： H01L25/07 ,  H01L23/049 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373 ,  H01L23/00

CPC分类号： H01L25/072 ,  H01L23/049 ,  H01L23/296 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/564 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/40139 ,  H01L2224/40225 ,  H01L2224/48096 ,  H01L2224/48139 ,  H01L2224/48225 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/14252

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a mounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

公开(公告)号：US20230326907A1

公开(公告)日：2023-10-12

申请号：US18296433

申请日：2023-04-06

申请人： Nexperia Technology (Shanghai) Ltd. ,  NEXPERIA B.V.

发明人： Wei Gong ,  Chunlin Zhu ,  Ke Jiang

IPC分类号： H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L23/34

CPC分类号： H01L25/072 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L23/49838 ,  H01L23/49811 ,  H01L23/34 ,  H01L2224/06181 ,  H01L2224/0603 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/49111 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2924/13055 ,  H01L2924/10272 ,  H01L2924/1033

摘要： A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.

公开(公告)号：US09881812B2

公开(公告)日：2018-01-30

申请号：US15227579

申请日：2016-08-03

申请人： ROHM CO., LTD.

发明人： Katsuhiko Yoshihara ,  Masao Saito

IPC分类号： H01L21/48 ,  H01L23/48 ,  H01L23/00 ,  H01L25/07 ,  H01L21/52 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L21/4825 ,  H01L21/52 ,  H01L23/48 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49861 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40225 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/8384 ,  H01L2224/84214 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00012

摘要： The power module includes: a first metallic circuit pattern, a semiconductor device disposed on the first metallic circuit pattern; a leadframe electrically connected to the semiconductor device; and a stress buffering layer disposed on an upper surface of the semiconductor device, and capable of buffering a CTE difference between the semiconductor device and the leadframe. The leadframe is connected to the semiconductor device via the stress buffering layer, a CTE of the stress buffering layer is equal to or less than a CTE of the leadframe, and a cross-sectional shape of the stress buffering layer is L-shape. There is provided: the power module capable of realizing miniaturization and large current capacity, and reducing cost thereof by using leadframe structure, and capable of reducing a variation in welding and improving a yield without damaging a semiconductor device; and a fabrication method for such a power module.

公开(公告)号：US20170084568A1

公开(公告)日：2017-03-23

申请号：US15126609

申请日：2014-04-04

申请人： Mitsubishi Electric Corporation

发明人： Masakazu TANI ,  Yoshiyuki DEGUCHI

IPC分类号： H01L23/00 ,  H01L23/367

CPC分类号： H01L24/40 ,  H01L23/3675 ,  H01L24/36 ,  H01L24/37 ,  H01L24/84 ,  H01L2224/37028 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/84205 ,  H01L2224/84801 ,  H01L2224/8482 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： In the semiconductor module according to the present invention, a conducting member which is used to electrically connect a semiconductor element arranged on a substrate or a bus bar with another electronic component is provided with a structure having flexibility capable of, in a junction with the semiconductor element, reducing the thermal stress due to difference in a coefficient of linear expansion between the conducting member and the semiconductor element, and absorbing dimensional error in objects to be connected. Therefore, the semiconductor module achieves both increased current capacity of the semiconductor device and improved reliability of the semiconductor module.

公开(公告)号：US20160343590A1

公开(公告)日：2016-11-24

申请号：US15227579

申请日：2016-08-03

申请人： ROHM CO., LTD.

发明人： Katsuhiko YOSHIHARA ,  Masao SAITO

IPC分类号： H01L21/48 ,  H01L25/065 ,  H01L21/52 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L21/4825 ,  H01L21/52 ,  H01L23/48 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49861 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40225 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/8384 ,  H01L2224/84214 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00012

摘要： The power module includes: a first metallic circuit pattern, a semiconductor device disposed on the first metallic circuit pattern; a leadframe electrically connected to the semiconductor device; and a stress buffering layer disposed on an upper surface of the semiconductor device, and capable of buffering a CTE difference between the semiconductor device and the leadframe. The leadframe is connected to the semiconductor device via the stress buffering layer, a CTE of the stress buffering layer is equal to or less than a CTE of the leadframe, and a cross-sectional shape of the stress buffering layer is L-shape. There is provided: the power module capable of realizing miniaturization and large current capacity, and reducing cost thereof by using leadframe structure, and capable of reducing a variation in welding and improving a yield without damaging a semiconductor device; and a fabrication method for such a power module.

摘要翻译： 功率模块包括：第一金属电路图案，设置在第一金属电路图案上的半导体器件; 电连接到所述半导体器件的引线框架; 以及应力缓冲层，其设置在所述半导体器件的上表面上，并且能够缓冲所述半导体器件与所述引线框架之间的CTE差。 引线框架经由应力缓冲层与半导体器件连接，应力缓冲层的CTE等于或小于引线框架的CTE，应力缓冲层的截面形状为L形。 提供了能够实现小型化和大电流容量的电力模块，并且通过使用引线框架结构来降低成本，并且能够减少焊接的变化并提高产量而不损坏半导体器件; 以及这种功率模块的制造方法。

公开(公告)号：US09379049B2

公开(公告)日：2016-06-28

申请号：US14409135

申请日：2013-05-27

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Hiroki Ikeuchi

IPC分类号： H01L23/495 ,  H01L23/433 ,  H01L23/64 ,  H02M7/00 ,  H01L23/373 ,  H01L25/07 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/49568 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/83851 ,  H01L2224/84205 ,  H01L2224/84801 ,  H01L2224/8482 ,  H01L2224/8485 ,  H01L2224/92247 ,  H01L2224/92248 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H02M7/003 ,  H01L2924/00 ,  H01L2224/83205 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01004 ,  H01L2924/00014

摘要： The semiconductor apparatus includes: the first lead frame; the second lead frame; the second insulation resin which is disposed between the first lead frame and the second lead frame; the sealing resin which seals the semiconductor elements, the first lead frame and the second lead frame; the electric wiring part which electrically connects the semiconductor elements and the first lead frame; and the interlayer connecting part which electrically connects the first lead frame and the second lead frame.

摘要翻译： 该半导体装置包括：第一引线框; 第二引线框架; 所述第二绝缘树脂设置在所述第一引线框架和所述第二引线框架之间; 密封半导体元件的密封树脂，第一引线框架和第二引线框架; 将所述半导体元件和所述第一引线框架电连接的所述电线路部分; 以及电连接第一引线框和第二引线框的层间连接部。

公开(公告)号：US09355950B1

公开(公告)日：2016-05-31

申请号：US14592244

申请日：2015-01-08

申请人： Infineon Technologies AG

发明人： Reinhold Bayerer

IPC分类号： H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L23/49833 ,  H01L23/49844 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40227 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/48227 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84205 ,  H01L2224/84214 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/85801 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： A power semiconductor module includes a metallization layer and a power semiconductor die attached to the metallization layer. The die has a first terminal and a second terminal disposed at a side of the die facing away from the metallization layer. The power semiconductor module further includes a first interconnect attached to the first terminal, a second interconnect attached to the second terminal and a flexible board including a first metal layer, a second metal layer and an insulator between the first and the second metal layers so that the first and the second metal layers are electrically insulated from one another. The first metal layer is attached to the first interconnect and the second metal layer is attached to the second interconnect such that the flexible board is spaced apart from the power semiconductor die by the first and the second interconnects.

摘要翻译： 功率半导体模块包括金属化层和附着到金属化层的功率半导体管芯。 模具具有第一端子和第二端子，该第一端子和第二端子布置在背离金属化层的模具的一侧。 功率半导体模块还包括附接到第一端子的第一互连件，附接到第二端子的第二互连件和在第一和第二金属层之间包括第一金属层，第二金属层和绝缘体的柔性板，使得 第一和第二金属层彼此电绝缘。 第一金属层附接到第一互连，第二金属层附接到第二互连，使得柔性板通过第一和第二互连与功率半导体管芯间隔开。