公开(公告)号：US07067909B2

公开(公告)日：2006-06-27

申请号：US10749096

申请日：2003-12-30

申请人： Rafael Reif ,  Nisha Checka ,  Anantha Chandrakasan

发明人： Rafael Reif ,  Nisha Checka ,  Anantha Chandrakasan

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/8383 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83205

摘要： A multi-layer integrated semiconductor structure is provided, which includes at least a first semiconductor structure and a second semiconductor structure coupled together via an interface. The interface includes at least a first portion adapted to provide a communication interface between the first semiconductor structure and the second semiconductor structure and at least a second portion adapted to reduce electrical interference between the first semiconductor structure and the second semiconductor structure.

摘要翻译： 提供了一种多层集成半导体结构，其包括经由界面耦合在一起的至少第一半导体结构和第二半导体结构。 接口包括至少第一部分，其适于提供第一半导体结构和第二半导体结构之间的通信接口，以及至少第二部分，其适于减小第一半导体结构和第二半导体结构之间的电干扰。

公开(公告)号：US20060087019A1

公开(公告)日：2006-04-27

申请号：US10749096

申请日：2003-12-30

申请人： Rafael Reif ,  Nisha Checka ,  Anantha Chandrakasan

发明人： Rafael Reif ,  Nisha Checka ,  Anantha Chandrakasan

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/8383 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83205

摘要： A multi-layer integrated semiconductor structure is provided, which includes at least a first semiconductor structure and a second semiconductor structure coupled together via an interface. The interface includes at least a first portion adapted to provide a communication interface between the first semiconductor structure and the second semiconductor structure and at least a second portion adapted to reduce electrical interference between the first semiconductor structure and the second semiconductor structure.

摘要翻译： 提供了一种多层集成半导体结构，其包括经由界面耦合在一起的至少第一半导体结构和第二半导体结构。 接口包括至少第一部分，其适于提供第一半导体结构和第二半导体结构之间的通信接口，以及至少第二部分，其适于减小第一半导体结构和第二半导体结构之间的电干扰。

公开(公告)号：US07480879B2

公开(公告)日：2009-01-20

申请号：US11400424

申请日：2006-04-07

申请人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

发明人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

摘要翻译： 公开了用于分析衬底噪声的系统和方法，其能够接受日益复杂和粒度的输入。 在早期阶段，该工具可以接受粗略的电路描述，例如门级网表。 该工具能够基于估计的管芯尺寸产生初步的衬底模型，从而允许设计人员早期指示潜在的衬底噪声问题。 在中间阶段，该工具可以接受更准确的电路描述，如SPICE网表。 可以生成更详细的衬底模型，其考虑布局信息，从而允许设计者在电路完成之前进行布局和电路修改。 最后，在最终验证期间，该工具可以接受更准确的网表，例如包括寄生电容的SPICE网表。 该工具还可以接受更详细的基板模型，并提供完成设计所需的基板噪声分析。

公开(公告)号：US20070067747A1

公开(公告)日：2007-03-22

申请号：US11400424

申请日：2006-04-07

申请人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

发明人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

摘要翻译： 公开了用于分析衬底噪声的系统和方法，其能够接受日益复杂和粒度的输入。 在早期阶段，该工具可以接受粗略的电路描述，例如门级网表。 该工具能够基于估计的管芯尺寸产生初步的衬底模型，从而允许设计人员早期指示潜在的衬底噪声问题。 在中间阶段，该工具可以接受更准确的电路描述，如SPICE网表。 可以生成更详细的衬底模型，其考虑布局信息，从而允许设计者在电路完成之前进行布局和电路修改。 最后，在最终验证期间，该工具可以接受更准确的网表，例如包括寄生电容的SPICE网表。 该工具还可以接受更详细的基板模型，并提供完成设计所需的基板噪声分析。

公开(公告)号：US20060099796A1

公开(公告)日：2006-05-11

申请号：US11312086

申请日：2005-12-20

申请人： Rafael Reif ,  Andy Fan

发明人： Rafael Reif ,  Andy Fan

IPC分类号： H01L21/4763

CPC分类号： H01L25/0657 ,  H01L23/5226 ,  H01L24/81 ,  H01L2221/68359 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/29147 ,  H01L2224/81011 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2224/0401

摘要： A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seam-less bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

摘要翻译： 形成多层半导体结构的方法包括在第一半导体的第一表面上提供具有第一预定厚度的图案化铜键合膜的第一层。 该方法还包括在第二半导体的第一表面上提供具有第二预定厚度的图案化铜键合膜的第二层。 第一和第二半导体结构可以对准，使得第一和第二图案化铜键合膜被设置在邻近处。 可以在第一和第二图案化铜键合膜之间形成虚拟的无缝接合，以提供第一和第二半导体作为多层半导体结构。

公开(公告)号：US06444509B1

公开(公告)日：2002-09-03

申请号：US08997326

申请日：1997-12-23

申请人： Takashi Noguchi ,  Rafael Reif ,  Julie Tsai ,  Andrew J. Tang

发明人： Takashi Noguchi ,  Rafael Reif ,  Julie Tsai ,  Andrew J. Tang

IPC分类号： H01L2100

CPC分类号： H01L29/66742 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/78684 ,  Y10S438/933

摘要： The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1−xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1−xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

摘要翻译： 本发明涉及一种具有栅极和有源区的高性能薄膜晶体管，其有源区包括多晶Si1-xGex合金材料和硅沟道层，其中沟道层硅介于 多晶Si1-xGex合金材料和栅极，以及制造这种高性能薄膜晶体管的方法。

公开(公告)号：US5828084A

公开(公告)日：1998-10-27

申请号：US411203

申请日：1995-03-27

申请人： Takashi Noguchi ,  Rafael Reif ,  Julie Tsai ,  Andrew J. Tang

发明人： Takashi Noguchi ,  Rafael Reif ,  Julie Tsai ,  Andrew J. Tang

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L29/04 ,  H01L29/76

CPC分类号： H01L29/66742 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/78684 ,  Y10S438/933

摘要： The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si.sub.1 -.sub.x Ge.sub.x alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si.sub.1-x Ge.sub.x alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

摘要翻译： 本发明涉及一种具有栅极和有源区的高性能薄膜晶体管，其有源区包括多晶Si1-xGex合金材料和硅沟道层，其中沟道层硅介于 多晶Si1-xGex合金材料和栅极，以及制造这种高性能薄膜晶体管的方法。

公开(公告)号：US07064055B2

公开(公告)日：2006-06-20

申请号：US10655670

申请日：2003-09-05

申请人： Rafael Reif ,  Andy Fan

发明人： Rafael Reif ,  Andy Fan

IPC分类号： H01L21/4763

CPC分类号： H01L25/0657 ,  H01L23/5226 ,  H01L24/81 ,  H01L2221/68359 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/29147 ,  H01L2224/81011 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2224/0401

摘要： A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seamless bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

摘要翻译： 形成多层半导体结构的方法包括在第一半导体的第一表面上提供具有第一预定厚度的图案化铜键合膜的第一层。 该方法还包括在第二半导体的第一表面上提供具有第二预定厚度的图案化铜键合膜的第二层。 第一和第二半导体结构可以对准，使得第一和第二图案化铜键合膜被设置在邻近处。 可以在第一和第二图案化铜键合膜之间形成几乎无缝的结合，以提供作为多层半导体结构的第一和第二半导体。

公开(公告)号：US06638797B2

公开(公告)日：2003-10-28

申请号：US10232700

申请日：2002-09-03

申请人： Takashi Noguchi ,  Rafael Reif ,  Julie Tsai ,  Andrew J. Tang

发明人： Takashi Noguchi ,  Rafael Reif ,  Julie Tsai ,  Andrew J. Tang

IPC分类号： H01L21339

CPC分类号： H01L29/66742 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/78684 ,  Y10S438/933

摘要： The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1-xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1-xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

摘要翻译： 本发明涉及一种具有栅极和有源区的高性能薄膜晶体管，其有源区包括多晶Si1-xGex合金材料和硅沟道层，其中沟道层硅介于 多晶Si1-xGex合金材料和栅极，以及制造这种高性能薄膜晶体管的方法。

公开(公告)号：US20080064183A1

公开(公告)日：2008-03-13

申请号：US11937184

申请日：2007-11-08

申请人： Rafael Reif ,  Kuan-Neng Chen ,  Chuan Tan ,  Andy Fan

发明人： Rafael Reif ,  Kuan-Neng Chen ,  Chuan Tan ,  Andy Fan

IPC分类号： H01L21/30

CPC分类号： H01L21/6835 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/8383 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83205

摘要： A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

摘要翻译： 形成多层半导体结构的方法包括使用第一界面将手柄构件附接到第一结构的顶表面。 蚀刻第一结构的底表面的至少一个区域以形成用于暴露限定在第一结构上的第一导电构件的一部分的至少第一通孔。 导电材料设置在第一通孔中，使得导电材料的第一端与第一导电构件电连通，并且导电材料的第二端在第一结构的底表面处露出。 第二接口设置在导电材料的至少第二端上，其用作在第一结构上限定的第一导电构件和多层半导体器件结构的第二结构之间的接合和/或电接口。