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    Substrate noise tool
    2.
    发明授权
    Substrate noise tool 失效
    基板噪音工具

    公开(公告)号：US07480879B2

    公开(公告)日：2009-01-20

    申请号：US11400424

    申请日：2006-04-07

    申请人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

    发明人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

    摘要翻译： 公开了用于分析衬底噪声的系统和方法，其能够接受日益复杂和粒度的输入。 在早期阶段，该工具可以接受粗略的电路描述，例如门级网表。 该工具能够基于估计的管芯尺寸产生初步的衬底模型，从而允许设计人员早期指示潜在的衬底噪声问题。 在中间阶段，该工具可以接受更准确的电路描述，如SPICE网表。 可以生成更详细的衬底模型，其考虑布局信息，从而允许设计者在电路完成之前进行布局和电路修改。 最后，在最终验证期间，该工具可以接受更准确的网表，例如包括寄生电容的SPICE网表。 该工具还可以接受更详细的基板模型，并提供完成设计所需的基板噪声分析。

    Substrate noise tool
    3.
    发明申请
    Substrate noise tool 失效
    基板噪音工具

    公开(公告)号：US20070067747A1

    公开(公告)日：2007-03-22

    申请号：US11400424

    申请日：2006-04-07

    申请人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

    发明人： Nisha Checka ,  Anantha Chandrakasan ,  Rafael Reif

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

    摘要翻译： 公开了用于分析衬底噪声的系统和方法，其能够接受日益复杂和粒度的输入。 在早期阶段，该工具可以接受粗略的电路描述，例如门级网表。 该工具能够基于估计的管芯尺寸产生初步的衬底模型，从而允许设计人员早期指示潜在的衬底噪声问题。 在中间阶段，该工具可以接受更准确的电路描述，如SPICE网表。 可以生成更详细的衬底模型，其考虑布局信息，从而允许设计者在电路完成之前进行布局和电路修改。 最后，在最终验证期间，该工具可以接受更准确的网表，例如包括寄生电容的SPICE网表。 该工具还可以接受更详细的基板模型，并提供完成设计所需的基板噪声分析。

    CIRCUIT AND METHOD TO STARTUP FROM VERY LOW VOLTAGES AND IMPROVE ENERGY HARVESTING EFFICIENCY IN THERMOELECTRIC HARVESTERS
    5.
    发明申请
    CIRCUIT AND METHOD TO STARTUP FROM VERY LOW VOLTAGES AND IMPROVE ENERGY HARVESTING EFFICIENCY IN THERMOELECTRIC HARVESTERS 有权
    从非常低的电压启动的电路和方法，并提高热电收割机的能源收集效率

    公开(公告)号：US20100270996A1

    公开(公告)日：2010-10-28

    申请号：US12577421

    申请日：2009-10-12

    申请人： Yogesh Ramadas ,  Anantha Chandrakasan

    发明人： Yogesh Ramadas ,  Anantha Chandrakasan

    IPC分类号： G05F3/08

    CPC分类号： H02M1/36

    摘要： An energy harvesting system is provided that includes a startup module for starting the energy harvesting system operation from a completely OFF state. The startup module uses mechanical vibrations due to motion to trigger a switch which permits the startup module to charge one or more first capacitive elements so to as reach a first defined voltage. A storage module buffers energy obtained from a thermoelectric harvester to be used by a load device. The storage module commences storing energy from the thermoelectric harvester when the first defined voltage has been reached allowing charging of one or more second capacitive elements to reach a second defined voltage. A DC-DC converter module provides regulated voltage to the load device after energy has been transferred from the thermoelectric harvester. The DC-DC converter module determines whether the second defined voltage has been reached and releases stored energy in the one or more first capacitive elements and the load device.

    摘要翻译： 提供能量收集系统，其包括用于从完全关闭状态启动能量收集系统操作的启动模块。 启动模块由于运动而使用机械振动来触发开关，其允许启动模块对一个或多个第一电容元件充电以便达到第一限定电压。 存储模块缓冲由热收缩机获得的能量，由负载装置使用。 当达到第一限定电压时，存储模块开始存储来自热电收集器的能量，允许一个或多个第二电容元件的充电达到第二限定电压。 DC-DC转换器模块在从热电收集器转移能量之后向负载装置提供调节电压。 DC-DC转换器模块确定是否已经达到第二定义电压，并释放一个或多个第一电容元件和负载装置中的存储能量。

    CIRCUIT AND METHOD TO IMPROVE ENERGY HARVESTING EFFICIENCY IN PIEZOELECTRIC HARVESTERS
    6.
    发明申请
    CIRCUIT AND METHOD TO IMPROVE ENERGY HARVESTING EFFICIENCY IN PIEZOELECTRIC HARVESTERS 有权
    提高压电式收割机能源收集效率的电路及方法

    公开(公告)号：US20100079034A1

    公开(公告)日：2010-04-01

    申请号：US12558820

    申请日：2009-09-14

    申请人： Yogesh Ramadass ,  Anantha Chandrakasan

    发明人： Yogesh Ramadass ,  Anantha Chandrakasan

    IPC分类号： H01L41/107

    CPC分类号： H02N2/181

    摘要： An energy harvester circuit is provided. The energy harvester circuit includes a harvesting module for extracting energy from an ambient source. A bias flip module manages the manner in which voltage across the harvesting module transitions when input current from the harvesting module changes direction so as to allow a majority of the charge available from the harvesting module to be extracted. A voltage transitioning module is shared amongst one or more DC-DC converters for efficient energy management.

    摘要翻译： 提供能量采集电路。 能量收集器电路包括用于从环境源提取能量的收集模块。 偏置翻转模块管理当来自收获模块的输入电流改变方向时收集模块上的电压转变的方式，以便允许从采集模块获得的大部分电荷被提取。 电压转换模块在一个或多个DC-DC转换器之间共享以实现有效的能量管理。

    Method and apparatus for compressing and decompressing a video image
    7.
    发明授权
    Method and apparatus for compressing and decompressing a video image 失效
    用于压缩和解压缩视频图像的方法和装置

    公开(公告)号：US5790269A

    公开(公告)日：1998-08-04

    申请号：US570765

    申请日：1995-12-12

    申请人： Ichiro Masaki ,  Ujjaval Desai ,  Anantha Chandrakasan ,  Berthold Horn

    发明人： Ichiro Masaki ,  Ujjaval Desai ,  Anantha Chandrakasan ,  Berthold Horn

    IPC分类号： G06T9/20 ,  H04N7/26 ,  H04N1/40

    CPC分类号： G06T9/20 ,  H04N19/20

    摘要： Edge or contour information is extracted from an image array by filtering and encoded. In order to improve reproduction accuracy, two separate filters are used to detect edge information. One of the filters detects "sharp" edges, or edges in which the discontinuity in pixel intensity values occurs over a range of a few pixels. The other filter detects "level" edges in which the pixel intensity value discontinuity occurs over a larger range of pixels than the "sharp" edges. The "smooth" areas between edges or contours are assumed to vary continuously between the contours, but for efficient implementation, a one-dimensional linear interpolation is used to regenerate the contour information between edges. In addition, to further improve performance, a line is fitted to the pixel intensity data. The end values of this line are then used for the pixel intensity data. In order to still further improve performance, the pixel intensity values associated with each contour are divided into groups and each group is then encoded. Another improvement is accomplished by mean coding the residual error.

    摘要翻译： 通过滤波和编码从图像阵列中提取边缘或轮廓信息。 为了提高再现精度，使用两个单独的滤波器来检测边缘信息。 其中一个滤波器检测“锐利”边缘，或者在几个像素范围内发生像素强度值不连续性的边缘。 另一个滤波器检测到像素强度值不连续发生在比“锐利”边缘更大的像素范围内的“电平”边缘。 假设边缘或轮廓之间的“平滑”区域在轮廓之间连续变化，但是为了有效实现，使用一维线性内插来重新生成边缘之间的轮廓信息。 此外，为了进一步提高性能，将线条拟合到像素强度数据。 然后将该行的结束值用于像素强度数据。 为了进一步提高性能，将与每个轮廓相关联的像素强度值分成组，然后对每个组进行编码。 另一个改进是通过平均编码残差来实现的。

    METHODS AND APPARATUS FOR REDUCING TIMING-SKEW ERRORS IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS
    9.
    发明申请
    METHODS AND APPARATUS FOR REDUCING TIMING-SKEW ERRORS IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS 有权
    用于减少时间间隔异或模数转换器中的时序误差的方法和装置

    公开(公告)号：US20160079994A1

    公开(公告)日：2016-03-17

    申请号：US14948875

    申请日：2015-11-23

    申请人： Sunghyuk Lee ,  Hae-Seung Lee ,  Anantha Chandrakasan

    发明人： Sunghyuk Lee ,  Hae-Seung Lee ,  Anantha Chandrakasan

    IPC分类号： H03M1/06 ,  H03M1/18 ,  H03M1/46 ,  H03M1/00 ,  H03M1/12

    CPC分类号： H03M1/0609 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/181 ,  H03M1/46

    摘要： A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

    摘要翻译： 时间交织（TI）模数转换器（ADC）架构采用低分辨率粗ADC通道，以奈奎斯特速率对输入模拟信号进行采样，便于定时偏移误差的背景校准，而不会中断对采样/ 转换输入信号。 粗ADC通道为多个更高分辨率TI ADC通道提供了时序参考，分别以较低的采样率采样输入信号。 将粗ADC数字输出与相应的TI ADC数字输出进行比较，可随时调整TI ADC通道的相应采样时钟，使其与粗ADC通道的采样时钟基本对齐，从而减少定时偏移误差。 在一个示例中，粗ADC输出提供相应TI ADC数字输出的最高有效位（MSB），以进一步提高转换速度并降低这些通道的功耗。

    Method and apparatus for reducing delay in a bus provided from parallel, capacitively coupled transmission lines
    10.
    发明授权
    Method and apparatus for reducing delay in a bus provided from parallel, capacitively coupled transmission lines 有权
    用于减少从并联的电容耦合传输线路提供的总线延迟的方法和装置

    公开(公告)号：US07400276B1

    公开(公告)日：2008-07-15

    申请号：US10351811

    申请日：2003-01-27

    申请人： Paul P. Sotiriadis ,  Anantha Chandrakasan

    发明人： Paul P. Sotiriadis ,  Anantha Chandrakasan

    IPC分类号： H03M7/00

    CPC分类号： H03M5/14 ,  H03M5/145

    摘要： A mechanism for use with a bus provided from parallel, capacitively-coupled bus lines to restrict a number of possible transitions on the bus to a number that is smaller than the maximum number of possible transitions so that data transmissions on the bus occur at a transmission rate which is higher than the transmission rate allowable if the number of transitions had not been restricted.

    摘要翻译： 一种用于由并联的电容耦合总线提供的总线的机制，用于将总线上的可能的转换数量限制在小于最大可能跳变数量的数量，使得总线上的数据传输发生在传输 如果没有限制转换次数，则该速率高于允许的传输速率。