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1.发明授权Method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog-to-digital converter (ADC) 有权包括模数转换器（ADC）在片上系统（SoC）集成电路中降低开关噪声的方法和装置，公开(公告)号：US07515076B1
公开(公告)日：2009-04-07
申请号：US11864876
申请日：2007-09-28
申请人： Rahul Singh , Prashanth Drakshapalli , Jie Fang , Edwin De Angel , Mohit Sood
发明人： Rahul Singh , Prashanth Drakshapalli , Jie Fang , Edwin De Angel , Mohit Sood
IPC分类号： H03M1/00
摘要： A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.
摘要翻译： 包括模数转换器（ADC）在内的片上系统（SoC）集成电路中降低开关噪声的方法和装置提供了ADC转换中降低的噪声。 ADC的采样电路通过采样时钟信号进行操作，数字电路和其他噪声发生电路（如电源转换器）由数字电路时钟信号进行操作。 这两组时钟信号由时钟发生器电路从相同的主时钟导出，但是在时钟发生器电路中施加偏移以使数字电路时钟信号的边缘远离对应于采样时钟的边缘的关键采样间隔 。 在一个实施例中，通过设置时钟发生器中的值来构成数字电路的一部分的处理器内核施加偏移，时钟发生器在暂停数字电路的时钟之后将其加载到分频器中。
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公开(公告)号：US07477178B1
公开(公告)日：2009-01-13
申请号：US11772132
申请日：2007-06-30
IPC分类号： H03M1/36
摘要： A power-optimized analog-to-digital converter (ADC) input circuit provides for optimized power consumption versus performance. The first amplifier stage of the ADC is provided by a plurality of amplifiers that are selectably enabled to provide a particular bandwidth and noise performance level. The selection of the combination of enabled amplifiers may be made in conformity with the sample rate of the converter and the amplifiers may have evenly-weighted bias currents, or unevenly weighed bias currents and may be optimized for their particular use in combinations for bandwidth and 1/f noise corner performance. The outputs of the amplifiers are combined in a combiner circuit, which may be a discrete-time chopping amplifier that receives charges from a plurality of capacitors that sample each enabled amplifier output.
摘要翻译： 功率优化的模数转换器（ADC）输入电路提供优化的功耗与性能。 ADC的第一放大级由多个放大器提供，其可选择地被实现以提供特定的带宽和噪声性能水平。 可以使得使能的放大器的组合的选择与转换器的采样率一致，并且放大器可以具有均匀加权的偏置电流或偏置电流不均匀，并且可以针对带宽和1的组合的特定用途进行优化 / f噪音角性能。 放大器的输出组合在组合器电路中，组合器电路可以是离散时间斩波放大器，其接收来自对每个使能的放大器输出采样的多个电容器的电荷。
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公开(公告)号：US08536854B2
公开(公告)日：2013-09-17
申请号：US12894472
申请日：2010-09-30
IPC分类号： G05F3/28
CPC分类号： G05F3/30
摘要： An electronic reference-signal generation system includes a supply invariant bandgap reference system that generates one or more bandgap reference signals that are substantially unaffected by bulk error currents. In at least one embodiment, the bandgap reference generates a substantially invariant bandgap reference signals for a range of direct current (DC) supply voltages. Additionally, in at least one embodiment, the bandgap reference system provides substantially invariant bandgap reference signals when the supply voltage varies due to alternating current (AC) voltages. In at least one embodiment, the bandgap reference system generates a bandgap reference voltage VBG, a “proportional to absolute temperature” (PTAT) current (“iPTAT”) and a “zero dependency on absolute temperature” (ZTAT) current (“iZTAT”) that are substantially unaffected by variations in the supply voltage and unaffected by a bulk error current.
摘要翻译： 电子参考信号生成系统包括供应不变带隙基准系统，其产生基本上不受体积误差电流影响的一个或多个带隙参考信号。 在至少一个实施例中，带隙参考产生用于一系列直流（DC）电源电压的基本上不变的带隙基准信号。 另外，在至少一个实施例中，当电源电压由于交流（AC）电压而变化时，带隙基准系统提供基本上不变的带隙基准信号。 在至少一个实施例中，带隙参考系统产生带隙参考电压VBG，“与绝对温度成比例”（PTAT）电流（“iPTAT”）和“对绝对温度的零依赖”（ZTAT）电流（“iZTAT” ），其基本上不受电源电压的变化影响并且不受体错误电流的影响。
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4.发明授权Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase reference application 有权具有多相参考应用的离散时间可编程增益模数转换器（ADC）输入电路公开(公告)号：US07489263B1
公开(公告)日：2009-02-10
申请号：US11864890
申请日：2007-09-28
IPC分类号： H03M1/12
摘要： A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase reference application, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled at the common mode voltage of the input, using one or more reference capacitor(s) that has been charged in a previous clock phase to the reference feedback voltage. The sampled input voltage is then applied in series with a quantizer-controlled reference voltage to the input of an integrator in a second clock phase. The summing mode of the integrator is maintained at the reference common-mode voltage. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high signal input impedance. Since the input voltage source is sampled with respect to its common-mode voltage, the common-mode input impedance is also high.
摘要翻译： 具有多相参考应用的离散时间可编程增益模数转换器（ADC）输入电路提供了基本上独立于输入电容大小和输入信号增益设置的高输入阻抗电平。 输入电压在输入的共模电压下采用一个或多个在先前的时钟相位被充电到参考反馈电压的参考电容。 然后将采样的输入电压与量化器控制的参考电压串联施加到第二时钟相位中的积分器的输入。 积分器的求和模式保持在参考共模电压。 由于从输入电压源拉出的电荷基本上仅由量化误差和输入噪声电压确定，所以电路具有高的信号输入阻抗。 由于输入电压源相对于其共模电压被采样，所以共模输入阻抗也很高。
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公开(公告)号：US20120081099A1
公开(公告)日：2012-04-05
申请号：US12894472
申请日：2010-09-30
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： An electronic reference-signal generation system includes a supply invariant bandgap reference system that generates one or more bandgap reference signals that are substantially unaffected by bulk error currents. In at least one embodiment, the bandgap reference generates a substantially invariant bandgap reference signals for a range of direct current (DC) supply voltages. Additionally, in at least one embodiment, the bandgap reference system provides substantially invariant bandgap reference signals when the supply voltage varies due to alternating current (AC) voltages. In at least one embodiment, the bandgap reference system generates a bandgap reference voltage VBG, a “proportional to absolute temperature” (PTAT) current (“iPTAT”) and a “zero dependency on absolute temperature” (ZTAT) current (“iZTAT”) that are substantially unaffected by variations in the supply voltage and unaffected by a bulk error current.
摘要翻译： 电子参考信号生成系统包括供应不变带隙基准系统，其产生基本上不受体积误差电流影响的一个或多个带隙参考信号。 在至少一个实施例中，带隙参考产生用于一系列直流（DC）电源电压的基本上不变的带隙基准信号。 另外，在至少一个实施例中，当电源电压由于交流（AC）电压而变化时，带隙基准系统提供基本上不变的带隙基准信号。 在至少一个实施例中，带隙参考系统产生带隙参考电压VBG，“与绝对温度成比例”（PTAT）电流（“iPTAT”）和“对绝对温度的零依赖”（ZTAT）电流（“iZTAT” ），其基本上不受电源电压的变化影响并且不受体错误电流的影响。
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6.发明授权Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling 有权具有输入信号和共模电流归零的离散时间可编程增益模数转换器（ADC）输入电路公开(公告)号：US07492296B1
公开(公告)日：2009-02-17
申请号：US11864884
申请日：2007-09-28
IPC分类号： H03M1/00
摘要： A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled using one or more reference capacitor(s) that have been charged with a net charge corresponding to a quantizer-controlled reference voltage in a preceding clock phase. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high input impedance. The reference capacitor(s) may be discharged in a third clock phase, so that input-signal-dependent voltages are discharged from the capacitor(s). An additional sampling capacitor can be discharged in the first clock phase and coupled in parallel with the reference capacitor during the second clock phase, to set the gain with respect to the input voltage.
摘要翻译： 具有输入信号和共模电流归零的离散时间可编程增益模数转换器（ADC）输入电路提供了基本上与输入电容大小和输入信号增益设置无关的高输入阻抗电平。 使用一个或多个参考电容对输入电压进行采样，该参考电容已经在前一时钟相位中与对应于量化器控制的参考电压的净电荷充电。 由于从输入电压源拉出的电荷基本上仅由量化误差和输入噪声电压确定，所以电路具有高的输入阻抗。 参考电容器可以在第三时钟相位中放电，使得输入信号相关电压从电容器放电。 在第二时钟相位期间，附加采样电容器可以在第一时钟相位放电并与参考电容并联耦合，以便相对于输入电压设置增益。
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