利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.022 秒)

    Scheduling tasks among processor cores
    1.
    发明授权
    Scheduling tasks among processor cores 有权
    处理器核心之间的调度任务

    公开(公告)号：US09207994B2

    公开(公告)日：2015-12-08

    申请号：US13997879

    申请日：2012-05-09

    申请人： Harinarayanan Seshadri ,  Rajeev Muralidhar ,  Vishwesh M. Rudramuni ,  Illyas Mansoor

    发明人： Harinarayanan Seshadri ,  Rajeev Muralidhar ,  Vishwesh M. Rudramuni ,  Illyas Mansoor

    IPC分类号： G06F9/00 ,  G06F1/32 ,  G06F9/50 ,  G06F1/20

    CPC分类号： G06F9/5094 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/00 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

    摘要： Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.

    摘要翻译： 本文描述了设备，计算机实现的方法，计算设备，系统和计算机可读介质（暂时性和非暂时性）的实施例，用于在多个处理器核之间调度多个任务。 计算设备的多个处理器核心的第一处理器核心可以被转换到屏蔽状态，其中没有新的任务被分配给第一处理器核心，并且执行已经分配给第一处理器核心的任务来完成， 以确定已经达到标准。 在各种实施例中，标准可以基于计算设备的状况，例如计算设备可用的功率或与计算设备相关联的温度。 在各种实施例中，在已经分配给第一处理器核心的任务执行完成之后，第一处理器核心可以转换到降低功率状态。

    SCHEDULING TASKS AMONG PROCESSOR CORES
    3.
    发明申请
    SCHEDULING TASKS AMONG PROCESSOR CORES 有权
    在处理器上调度任务

    公开(公告)号：US20130318379A1

    公开(公告)日：2013-11-28

    申请号：US13997879

    申请日：2012-05-09

    申请人： Harinarayanan Seshadri ,  Rajeev Muralidhar ,  Vishwesh M. Rudramuni ,  Illyas Mansoor

    发明人： Harinarayanan Seshadri ,  Rajeev Muralidhar ,  Vishwesh M. Rudramuni ,  Illyas Mansoor

    IPC分类号： G06F9/50 ,  G06F1/32

    CPC分类号： G06F9/5094 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/00 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

    摘要： Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.

    摘要翻译： 本文描述了设备，计算机实现的方法，计算设备，系统和计算机可读介质（暂时性和非暂时性）的实施例，用于在多个处理器核之间调度多个任务。 计算设备的多个处理器核心的第一处理器核心可以被转换到屏蔽状态，其中没有新的任务被分配给第一处理器核心，并且执行已经分配给第一处理器核心的任务来完成， 以确定已经达到标准。 在各种实施例中，标准可以基于计算设备的状况，例如计算设备可用的功率或与计算设备相关联的温度。 在各种实施例中，在已经分配给第一处理器核心的任务执行完成之后，第一处理器核心可以转变到降低功率状态。

    CONSTRAINED BOOT TECHNIQUES IN MULTI-CORE PLATFORMS
    4.
    发明申请
    CONSTRAINED BOOT TECHNIQUES IN MULTI-CORE PLATFORMS 有权
    多核平台中的约束引导技术

    公开(公告)号：US20140115368A1

    公开(公告)日：2014-04-24

    申请号：US14125497

    申请日：2012-09-27

    申请人： Rajeev Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni

    发明人： Rajeev Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

    摘要： Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that controls which specific core(s) are to be powered up/down and/or which power state these core(s) need to enter based, at least in part, on input from OS and/or software application(s). Other embodiments are also claimed and disclosed.

    摘要翻译： 描述与多核平台中约束启动技术有关的方法和设备。 在一个实施例中，处理器可以包括逻辑，至少部分地基于来自OS和OS的输入来控制哪些特定核心被上电/下电和/或这些核心需要进入的哪个功率状态 /或软件应用程序。 还要求和公开其它实施例。