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公开(公告)号：US08604540B2
公开(公告)日：2013-12-10
申请号：US12956152
申请日：2010-11-30
IPC分类号： H01L29/66 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/8128
摘要： A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.
摘要翻译： 具有JFET，MESFET或MOSFET的宽带隙半导体器件主要包括半导体衬底，第一导电类型半导体层和第一导电型沟道层。 半导体层形成在基板的主表面上。 在半导体层中以半导体层被分成源极区和漏极区的方式形成凹部。 凹部具有由基板的主表面和由半导体层限定的侧壁限定的底部。 沟道层的杂质浓度低于半导体层的杂质浓度。 沟槽层通过外延生长形成在凹部的底部和侧壁上。
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公开(公告)号：US08575648B2
公开(公告)日：2013-11-05
申请号：US12976116
申请日：2010-12-22
IPC分类号： H01L29/423 , H01L21/337
CPC分类号： H01L29/0847 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.
摘要翻译： 具有JFET或MOSFET的碳化硅半导体器件包括半导体衬底和沟槽。 半导体衬底具有碳化硅衬底，碳化硅衬底上的漂移层，漂移层上的第一栅极区域和第一栅极区域上的源极区域。 沟槽具有纵向方向的带状，并通过穿透源极区域和第一栅极区域而到达漂移层。 在沟道层上填充沟道层和第二栅极区域。 源极区域不位于沟槽的纵向方向的端部。
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3.发明申请公开(公告)号：US20110156054A1
公开(公告)日：2011-06-30
申请号：US12976116
申请日：2010-12-22
IPC分类号： H01L29/24 , H01L21/337 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.
摘要翻译： 具有JFET或MOSFET的碳化硅半导体器件包括半导体衬底和沟槽。 半导体衬底具有碳化硅衬底，碳化硅衬底上的漂移层，漂移层上的第一栅极区域和第一栅极区域上的源极区域。 沟槽具有纵向方向的带状，并通过穿透源极区域和第一栅极区域而到达漂移层。 在沟道层上填充沟道层和第二栅极区域。 源极区域不位于沟槽的纵向方向的端部。
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4.发明申请公开(公告)号：US20110156052A1
公开(公告)日：2011-06-30
申请号：US12926894
申请日：2010-12-16
IPC分类号： H01L29/24 , H01L29/80 , H01L21/337
CPC分类号： H01L29/808 , H01L29/045 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region.
摘要翻译： 具有JFET的半导体器件包括：由半绝缘半导体材料制成的衬底; 在所述基板的表面部分中的栅极区域; 设置在栅区上并与其接触的沟道区; 源极区域和漏极区域，分别设置在栅极区域的两侧，以夹持沟道区域; 源极，与源极电耦合; 漏极，与漏极区电耦合; 以及与栅极区域电耦合的栅电极。 源极区域和漏极区域中的每一个的杂质浓度高于沟道区域的杂质浓度。
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5.发明授权Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate 有权一种在碳化硅半导体衬底中制造具有沟槽的半导体器件的方法公开(公告)号：US07241694B2
公开(公告)日：2007-07-10
申请号：US11105587
申请日：2005-04-14
IPC分类号： H01L21/18 , H01L21/302 , H01L21/308
CPC分类号： H01L29/045 , H01L29/66068 , H01L29/7828 , H01L29/8083
摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.
摘要翻译： 一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除 比1600℃
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6.发明授权Semiconductor device having D mode JFET and E mode JFET and method for manufacturing the same 有权具有D型JFET和E型JFET的半导体器件及其制造方法公开(公告)号：US08373209B2
公开(公告)日：2013-02-12
申请号：US12974516
申请日：2010-12-21
IPC分类号： H01L29/12
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.
摘要翻译： 半导体器件包括：衬底; 以及耗尽和增强型JFET。 耗尽型JFET包括：衬底上的凹面; 凹陷中的沟道层; 沟道层上的第一栅极区; 在沟道层中的第一栅极区域的相应侧上的第一源极和漏极区域; 第一栅极，源极和漏极。 增强模式JFET包括：在衬底上的凸起; 沟道层上凸; 沟道层上的第二栅极区; 在沟道层中的第二栅极区的相应侧上的第二源极和漏极区; 第二栅极，源极和漏极。 凹槽中的沟道层的厚度大于沟槽层的厚度。
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7.发明申请SEMICONDUCTOR DEVICE HAVING D MODE JFET AND E MODE JFET AND METHOD FOR MANUFACTURING THE SAME 有权具有D模式JFET和E模式JFET的半导体器件及其制造方法公开(公告)号：US20110156053A1
公开(公告)日：2011-06-30
申请号：US12974516
申请日：2010-12-21
IPC分类号： H01L29/12 , H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.
摘要翻译： 半导体器件包括：衬底; 以及耗尽和增强型JFET。 耗尽型JFET包括：衬底上的凹面; 凹陷中的沟道层; 沟道层上的第一栅极区; 在沟道层中的第一栅极区域的相应侧上的第一源极和漏极区域; 第一栅极，源极和漏极。 增强模式JFET包括：在衬底上的凸起; 沟道层上凸; 沟道层上的第二栅极区; 在沟道层中的第二栅极区的相应侧上的第二源极和漏极区; 第二栅极，源极和漏极。 凹槽中的沟道层的厚度大于沟槽层的厚度。
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公开(公告)号：US08194392B2
公开(公告)日：2012-06-05
申请号：US12830517
申请日：2010-07-06
IPC分类号： H01G4/06
CPC分类号： H01G4/1227 , C04B35/4682 , C04B35/49 , C04B35/495 , C04B2235/3206 , C04B2235/3215 , C04B2235/3236 , C04B2235/3255 , C04B2235/3279 , C04B2235/3284 , C04B2235/3298 , C04B2235/656 , C04B2235/6567 , C04B2235/662 , C04B2235/77 , C04B2235/81 , H01G4/0085 , H01G4/30
摘要： A ceramic material has a perovskite structure and is represented by formula of (1−x)ABO3-xYZO3. In the formula, “x” is a real number that is greater than 0 and is less than 1 each of “A,” “B,” “Y,” and “Z” is one or more kinds selected from a plurality of metal ions M other than a Pb ion and alkali metal ions, “A” is bivalent, “B” is tetravalent, “Y” is trivalent or combination of trivalent metal ions, and “Z” is bivalent and/or trivalent metal ions, or a bivalent and/or pentavalent metal ions.
摘要翻译： 陶瓷材料具有钙钛矿结构并由（1-x）ABO 3-x YZO 3的式表示。 在该公式中，“x”是大于0并且小于“A”，“B”，“Y”“的1的实数，”Z“是从多个金属中选择的一种或多种 离子M除了Pb离子和碱金属离子之外，“A”为二价，“B”为四价，“Y”为三价金属离子或三价金属离子的组合，“Z”为二价和/或三价金属离子，或 二价和/或五价金属离子。
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9.发明授权公开(公告)号：US08274086B2
公开(公告)日：2012-09-25
申请号：US12458968
申请日：2009-07-28
IPC分类号： H01L29/15 , H01L31/0256
CPC分类号： H01L29/8083 , H01L29/063 , H01L29/0692 , H01L29/6609 , H01L29/66325 , H01L29/8611 , H01L29/872
摘要： A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
摘要翻译： 宽带隙半导体器件具有晶体管单元区域，二极管形成区域，位于晶体管单元区域和二极管形成区域之间的电场弛豫区域以及围绕晶体管单元区域和二极管形成区域的外围区域。 在晶体管单元区域中，设置结型场效应晶体管。 在二极管形成区域中，设置二极管。 在电场弛豫区域中，设置隔离部。 隔离部分包括分隔晶体管单元区域和二极管形成区域的沟槽，设置在沟槽的内壁上的第一导电类型层和设置在第一导电类型层的表面上的第二导电类型层 以填补沟槽。 第一导电型层和第二导电型层提供PN结。
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10.发明申请公开(公告)号：US20100025693A1
公开(公告)日：2010-02-04
申请号：US12458968
申请日：2009-07-28
IPC分类号： H01L29/772 , H01L29/02
CPC分类号： H01L29/8083 , H01L29/063 , H01L29/0692 , H01L29/6609 , H01L29/66325 , H01L29/8611 , H01L29/872
摘要： A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
摘要翻译： 宽带隙半导体器件具有晶体管单元区域，二极管形成区域，位于晶体管单元区域和二极管形成区域之间的电场弛豫区域以及围绕晶体管单元区域和二极管形成区域的外围区域。 在晶体管单元区域中，设置结型场效应晶体管。 在二极管形成区域中，设置二极管。 在电场弛豫区域中，设置隔离部。 隔离部分包括分隔晶体管单元区域和二极管形成区域的沟槽，设置在沟槽的内壁上的第一导电类型层和设置在第一导电类型层的表面上的第二导电类型层 以填补沟槽。 第一导电型层和第二导电型层提供PN结。
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