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公开(公告)号：US06909137B2
公开(公告)日：2005-06-21
申请号：US10249406
申请日：2003-04-07
IPC分类号： H01L21/20 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864
摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.
摘要翻译： 本发明包括一种方法，包括提供基底的步骤; 在衬底中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。 本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。
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公开(公告)号：US07439128B2
公开(公告)日：2008-10-21
申请号：US11124324
申请日：2005-05-06
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864
摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.
摘要翻译： 本发明包括一种方法，包括提供基底的步骤; 在基板中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。 本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。
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3.发明申请SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION: METHOD AND STRUCTURE 有权简化的垂直阵列设备DRAM / eDRAM集成：方法和结构公开(公告)号：US20060226481A1
公开(公告)日：2006-10-12
申请号：US10907630
申请日：2005-04-08
IPC分类号： H01L27/12
CPC分类号： H01L27/12 , H01L27/10841 , H01L27/10891
摘要： The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.
摘要翻译： 本发明提供一种半导体结构，其包括位于半导体存储器件上方的有源字线和位于所述有源字线附近并位于衬底的有效区域之上的被动字线。 根据本发明，被动字线通过衬垫氮化物与有源区分离。 本发明还提供了能够形成本发明的半导体结构的方法。
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4.发明授权Simplified vertical array device DRAM/eDRAM integration: method and structure 有权简化垂直阵列器件DRAM / eDRAM集成：方法和结构公开(公告)号：US07485910B2
公开(公告)日：2009-02-03
申请号：US10907630
申请日：2005-04-08
IPC分类号： H01L27/108
CPC分类号： H01L27/12 , H01L27/10841 , H01L27/10891
摘要： The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.
摘要翻译： 本发明提供一种半导体结构，其包括位于半导体存储器件上方的有源字线和位于所述有源字线附近并位于衬底的有效区域之上的被动字线。 根据本发明，被动字线通过衬垫氮化物与有源区分离。 本发明还提供了能够形成本发明的半导体结构的方法。
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公开(公告)号：US20050196932A1
公开(公告)日：2005-09-08
申请号：US11124324
申请日：2005-05-06
IPC分类号： H01L21/20 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864
摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.
摘要翻译： 本发明包括一种方法，包括提供基底的步骤; 在衬底中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。 本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。
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6.发明授权Forming collar structures in deep trench capacitors with thermally stable filler material 失效在具有热稳定的填充材料的深沟槽电容器中形成套环结构公开(公告)号：US06967137B2
公开(公告)日：2005-11-22
申请号：US10604255
申请日：2003-07-07
IPC分类号： H01L21/20 , H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： In the course of forming the collar dielectric in a DRAM cell having a deep trench capacitor, a number of filling and stripping steps required in the prior art are eliminated by the use of a spin-on material that can withstand the high temperatures required in front-end processing and also provide satisfactory filling ability and etch resistance. The use of atomic layer deposition for the formation of the collar dielectric reduces the need for a high temperature anneal of the fill material and reduces the amount of outgassing or cracking.
摘要翻译： 在具有深沟槽电容器的DRAM单元中形成环形电介质的过程中，现有技术中所需要的许多填充和剥离步骤通过使用可承受前面所需的高温的旋涂材料而消除 并且提供令人满意的填充能力和耐蚀刻性。 用于形成套环电介质的原子层沉积减少了填充材料的高温退火的需要并减少了除气或开裂的量。
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公开(公告)号：US08643061B2
公开(公告)日：2014-02-04
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L29/66
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译： 提供半导体结构。 该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。
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公开(公告)号：US08557652B2
公开(公告)日：2013-10-15
申请号：US13608422
申请日：2012-09-10
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.
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9.发明申请公开(公告)号：US20130019944A1
公开(公告)日：2013-01-24
申请号：US13188214
申请日：2011-07-21
申请人： Bahman Hekmatshoar-Tabari , Marinus Hopstaken , Dae-Gyu Park , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Bahman Hekmatshoar-Tabari , Marinus Hopstaken , Dae-Gyu Park , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0376
CPC分类号： H01L31/03762 , H01L31/02167 , H01L31/075 , H01L31/1864 , H01L31/202 , Y02E10/548 , Y02P70/521
摘要： A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.
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10.发明申请APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS 有权聚束光束植入用于制造阈值电压调节FET的应用公开(公告)号：US20120187502A1
公开(公告)日：2012-07-26
申请号：US13432716
申请日：2012-03-28
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.
摘要翻译： 提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。 所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从 聚束束植入步骤后的结构。
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