公开(公告)号：US07030012B2

公开(公告)日：2006-04-18

申请号：US10708530

申请日：2004-03-10

申请人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

发明人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

IPC分类号： H01L21/44

CPC分类号： H01L27/10894 ,  H01L27/10861 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region is formed by the following steps. Form a sacrificial polysilicon layer over the array region. Form a blanket gate oxide layer over the device. Form a thick deposit of polysilicon in both the array region where word lines are located and in the support region where the logic circuits are located. Remove the thick polysilicon layer, the gate oxide layer and the sacrificial polysilicon layer only in the array region. Then deposit a thin polysilicon layer in both the array region and support regions. Next deposit a metallic conductor coating including at least an elemental metal layer portion over the thin polysilicon layer. Then form word lines and sate electrodes in the array region and support region respectively.

摘要翻译： 包括至少一个半导体存储器阵列区域和包括支撑区域的逻辑电路的集成电路器件通过以下步骤形成。 在阵列区域上形成牺牲多晶硅层。 在器件上形成覆盖栅极氧化物层。 在字线位于的阵列区域和逻辑电路所在的支撑区域中形成厚多晶硅沉积物。 仅在阵列区域中去除厚的多晶硅层，栅极氧化物层和牺牲多晶硅层。 然后在阵列区域和支撑区域中沉积薄多晶硅层。 接着在薄多晶硅层上沉积至少包含元素金属层部分的金属导体涂层。 然后分别在阵列区域和支撑区域中形成字线和基极。

公开(公告)号：US20050202672A1

公开(公告)日：2005-09-15

申请号：US10708530

申请日：2004-03-10

申请人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

发明人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L27/10894 ,  H01L27/10861 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprised of at least one semiconductor memory array and logic circuits. The memory array includes electrically conductive word lines. The logic circuits include logic transistors with electrically conductive gates. The gates of the logic transistors and the word lines are composed of polysilicon and a metal layer. The metal layer is thicker than the polysilicon layer in the word lines; and the metal layer is thinner than the polysilicon layer in the gates of the logic transistors.

摘要翻译： 一种由至少一个半导体存储器阵列和逻辑电路组成的集成电路。 存储器阵列包括导电字线。 逻辑电路包括具有导电栅极的逻辑晶体管。 逻辑晶体管和字线的栅极由多晶硅和金属层组成。 金属层比字线中的多晶硅层厚; 并且金属层比逻辑晶体管的栅极中的多晶硅层薄。

公开(公告)号：US06908806B2

公开(公告)日：2005-06-21

申请号：US10355726

申请日：2003-01-31

申请人： Haining Yang ,  Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Rajeev Malik ,  Hongwen Yan ,  Ravikumar Ramachandran

发明人： Haining Yang ,  Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Rajeev Malik ,  Hongwen Yan ,  Ravikumar Ramachandran

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/76838

摘要： A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

摘要翻译： 一种制造半导体器件的方法，该半导体器件具有包括栅极叠层侧壁的栅极叠层结构，栅叠层结构具有一个或多个包含栅极金属的金属层。 栅极金属通过化学蚀刻从栅极堆叠侧壁凹入。 门堆叠结构的栅极金属被选择性地氧化以形成至少部分地填充凹部的金属氧化物。

公开(公告)号：US06509226B1

公开(公告)日：2003-01-21

申请号：US09670741

申请日：2000-09-27

申请人： Venkatachalam C. Jaiprakash ,  Jack Mandelman ,  Ramachandra Divakaruni ,  Rajeev Malik ,  Mihel Seitz

发明人： Venkatachalam C. Jaiprakash ,  Jack Mandelman ,  Ramachandra Divakaruni ,  Rajeev Malik ,  Mihel Seitz

IPC分类号： H01L218242

CPC分类号： H01L27/10861

摘要： Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.

摘要翻译： 包含垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体（GC）多晶硅平坦化到顶部氧化物的顶表面进行。 在平坦化表面上沉积薄多晶硅层，并沉积有源区（M）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 M掩模用于将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽。 执行AA氧化，隔离沟槽填充有高密度等离子体（HDP）氧化物，并且平坦化到AA衬垫氮化物的顶表面。 在隔离沟槽（IT）平坦化之后，剥离AA衬垫氮化物，薄硅层用作保护底层氧化物的蚀刻停止层。 沉积蚀刻载体（ES）氮化物衬垫，并且将ES掩模图案化以打开支撑区域。 从暴露的区域蚀刻ES氮化物，薄多晶硅层和顶部氧化物。 牺牲氧化与井注入一起施加，支持栅极氧化和支撑栅极多晶硅沉积。 使用蚀刻阵列（EA）掩模，在阵列中打开支撑栅极多晶硅。 对于下层硅层选择性地除去ES氮化物，保护顶部氧化物。 沉积栅极堆叠并图案化，并且该工艺继续完成。

公开(公告)号：US06541810B2

公开(公告)日：2003-04-01

申请号：US09896741

申请日：2001-06-29

申请人： Ramachandra Divakaruni ,  Prakash Dev ,  Rajeev Malik ,  Larry Nesbit

发明人： Ramachandra Divakaruni ,  Prakash Dev ,  Rajeev Malik ,  Larry Nesbit

IPC分类号： H01L27108

CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10891

摘要： The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

摘要翻译： 用于形成动态随机存取存储器的垂直MOSFET结构包括包括一个或多个氮化硅间隔物的栅堆叠结构; 设置在阵列沟槽中的垂直栅极多晶硅区域，其中所述垂直栅极多晶硅区域包括一个或多个氮化硅间隔物; 位线扩散区; 与阵列沟槽接壤的浅沟槽隔离区; 并且其中栅极堆叠结构设置在垂直栅极多晶硅区域上，使得栅极堆叠结构和垂直栅极多晶硅区域的氮化硅间隔物与位线扩散区域和浅沟槽隔离区域形成无边界接触。 垂直栅极多晶硅通过氮化物间隔物从位线扩散和浅沟槽隔离区域隔离，这提供了减少的位线电容并且减少了位线扩散到垂直栅极短路的入射。

公开(公告)号：US09515140B2

公开(公告)日：2016-12-06

申请号：US12015272

申请日：2008-01-16

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L29/73 ,  H01L29/10 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。

公开(公告)号：US08703552B2

公开(公告)日：2014-04-22

申请号：US13419624

申请日：2012-03-14

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L27/06 ,  H01L21/8242

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181

摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

摘要翻译： 提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。 在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。 沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。 第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。 第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。 在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。 还提供了一种用于形成上述装置的方法。

公开(公告)号：US08492818B2

公开(公告)日：2013-07-23

申请号：US12881481

申请日：2010-09-14

申请人： Keith Kwong Hon Wong ,  Ramachandra Divakaruni ,  Roger A. Booth, Jr.

发明人： Keith Kwong Hon Wong ,  Ramachandra Divakaruni ,  Roger A. Booth, Jr.

IPC分类号： H01L27/108

CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10867 ,  H01L29/945

摘要： A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.

摘要翻译： 双节点介质沟槽电容器包括在沟槽中形成的一叠层。 层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。 双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。 第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。 双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

公开(公告)号：US20120256267A1

公开(公告)日：2012-10-11

申请号：US13080019

申请日：2011-04-05

申请人： Ying Li ,  Ramachandra Divakaruni

发明人： Ying Li ,  Ramachandra Divakaruni

IPC分类号： H01L27/06 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L23/5256 ,  H01L27/0629 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.

摘要翻译： 提供一种用于制造电熔丝和场效应晶体管的方法，所述场效应晶体管具有金属栅极，该金属栅极包括从覆盖衬底的电介质区域中的第一和第二开口去除材料，其中第一开口与衬底的有源半导体区域对准， 并且所述第二开口与所述衬底的隔离区域对准，并且所述有源半导体区域包括与所述第一开口的边缘相邻的源极区域和漏极区域。 可以形成电熔丝，其具有填充第二开口的熔丝元件，熔丝元件是单一导电材料的整体区域，金属或金属的导电化合物。 可以形成在第一开口内延伸的金属栅极，以限定包括金属栅极和有源半导体区域的场效应晶体管（FET）。

公开(公告)号：US08236634B1

公开(公告)日：2012-08-07

申请号：US13050023

申请日：2011-03-17

申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L27/088

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。