公开(公告)号：US20060098737A1

公开(公告)日：2006-05-11

申请号：US10539898

申请日：2003-11-20

申请人： Ramanathan Sethuraman ,  Fabian Ernst ,  Patrick Meuwissen ,  Harm Johannes Antonius Peters ,  Rafael Peset Llopis

发明人： Ramanathan Sethuraman ,  Fabian Ernst ,  Patrick Meuwissen ,  Harm Johannes Antonius Peters ,  Rafael Peset Llopis

IPC分类号： H04N11/02 ,  H04N7/12 ,  H04B1/66 ,  H04N11/04

CPC分类号： G06T7/20 ,  G06T7/223 ,  H04N19/20 ,  H04N19/51

摘要： A method to determine motion vectors for respective segments (S11-S14) of a segmented image (100) comprises: creating sets of candidate motion vectors for the respective segments (S11-S14); dividing the segmented image (100) into a grid of blocks (b11-b88) of pixels; determining for the blocks (b11-b88) of pixels which of the candidate motion vectors belong to the blocks (b11-b88), on basis of the segments (S11-S14) and the locations of the blocks (b11-b88) within the segmented image (100); computing partial match errors for the blocks (b11-b88) on basis of the determined candidate motion vectors and on basis of pixel values of a further image (102); combining the partial match errors into a number of match errors per segment; selecting for each of the sets of candidate motion vectors respective candidate motion vectors on basis of the match errors; and assigning the selected candidate motion vectors as the motion vectors for the respective segments (S11-S14).

摘要翻译： 确定分割图像（100）的各个段（S 11 -S 14）的运动矢量的方法包括：为各个段创建候选运动矢量集合（S 11 -S 14）; 将分割图像（100）划分成像素的块（b 11 -b 88）的网格; 基于片段（S 11 -S 14）和块的位置（S 11 -S 14），确定候选运动矢量中属于块（b 11 -b 88）的像素的块（b 11 -b88） b 11 -b 88）; 基于所确定的候选运动矢量和基于另一图像（102）的像素值来计算块（b 11 -b 88）的部分匹配误差; 将部分匹配错误组合成每个段的多个匹配错误; 基于匹配误差来选择候选运动矢量各个候选运动矢量中的每一组; 并且将所选择的候选运动矢量分配为各个段的运动矢量（S 11 -S 14）。

公开(公告)号：US20050273569A1

公开(公告)日：2005-12-08

申请号：US10530375

申请日：2003-09-17

申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3802 ,  G06F9/3853

摘要： A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

摘要翻译： 用VLIW数据处理装置执行指令字的程序。 该装置包括能够并行地从每个指令字执行多个指令的多个功能单元。 来自各个指令字中的至少一些的指令被并行地从相应的存储器单元中取出，用功能单元共用的指令地址寻址。 将指令地址转换为物理地址可以针对一个或多个特定存储器单元进行修改。 修改由程序中的修改更新指令控制。 因此，可以根据程序执行来选择来自存储器单元的指令将响应于指令地址而组合到指令字中。

公开(公告)号：US20130138927A1

公开(公告)日：2013-05-30

申请号：US13751324

申请日：2013-01-28

申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

IPC分类号： G06F9/30

CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

摘要翻译： 数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。 指令执行单元，并行地从指令字处理多个指令。 检测单元，检测指示地址所在的多个范围中的哪一个。 检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。 在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。

公开(公告)号：US07664929B2

公开(公告)日：2010-02-16

申请号：US10530375

申请日：2003-09-17

申请人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman ,  Srinivasan Balakrishnan ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

发明人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman ,  Srinivasan Balakrishnan ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3853

摘要： A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

摘要翻译： 用VLIW数据处理装置执行指令字的程序。 该装置包括能够并行地从每个指令字执行多个指令的多个功能单元。 来自各个指令字中的至少一些的指令被并行地从相应的存储器单元中取出，用功能单元共用的指令地址寻址。 将指令地址转换为物理地址可以针对一个或多个特定存储器单元进行修改。 修改由程序中的修改更新指令控制。 因此，可以根据程序执行来选择来自存储器单元的指令将响应于指令地址而组合到指令字中。

公开(公告)号：US20060004986A1

公开(公告)日：2006-01-05

申请号：US10530495

申请日：2003-10-01

申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Johannes Peters ,  Rafael Peset Llopis

发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Johannes Peters ,  Rafael Peset Llopis

IPC分类号： G06F15/00 ,  G06F12/00

CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

公开(公告)号：US08364935B2

公开(公告)日：2013-01-29

申请号：US10530495

申请日：2003-10-01

申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

摘要翻译： 数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。 指令执行单元，并行地从指令字处理多个指令。 检测单元，检测指示地址所在的多个范围中的哪一个。 检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。 在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。

公开(公告)号：US07457970B2

公开(公告)日：2008-11-25

申请号：US10530639

申请日：2003-09-17

申请人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

发明人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

IPC分类号： G06F1/00

CPC分类号： G06F9/3853 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30167 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.

摘要翻译： 数据处理装置具有指令存储器系统，其被布置为输出能够包含多个指令的指令字，响应于相应的指令地址输出相应的指令字。 指令执行单元包含多个功能单元，每个功能单元能够执行来自指令字的相应指令，并且与其他功能单元从指令字执行其他指令并行执行。 提供省电电路以将功能单元和/或指令存储器的可选择子集切换到省电状态，而指令存储器的其他功能单元和部分在正常功耗状态下继续处理指令。 省电电路根据程序执行选择指令存储器的功能单元和/或部分。

公开(公告)号：US20060156004A1

公开(公告)日：2006-07-13

申请号：US10530639

申请日：2003-09-17

申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

IPC分类号： H04N17/00

CPC分类号： G06F9/3853 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30167 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.

摘要翻译： 数据处理装置具有指令存储器系统，其被布置为输出能够包含多个指令的指令字，响应于相应的指令地址输出相应的指令字。 指令执行单元包含多个功能单元，每个功能单元能够执行来自指令字的相应指令，并且与其他功能单元从指令字执行其他指令并行执行。 提供省电电路以将功能单元和/或指令存储器的可选择子集切换到省电状态，而指令存储器的其他功能单元和部分在正常功耗状态下继续处理指令。 省电电路根据程序执行选择指令存储器的功能单元和/或部分。

公开(公告)号：US20070019874A1

公开(公告)日：2007-01-25

申请号：US10570546

申请日：2004-08-26

申请人： Ramanathan Sethuraman ,  Fabian Ernst

发明人： Ramanathan Sethuraman ,  Fabian Ernst

IPC分类号： G06K9/36

CPC分类号： H04N19/428 ,  H04N19/39 ,  H04N21/2343 ,  H04N21/2662 ,  H04N21/4402 ,  H04N21/4621

摘要： The invention relates to content signal processing and in particular to processing of a video content signal. An apparatus (100) for content signal processing comprises a scalable encoder (101) for encoding a content signal to generate scalable encoded data comprising data associated with a plurality of compression rates. A compression processor (105) determines compression factor indicators indicating data associated with the plurality of compression rates. Thus, the compression factor indicators indicate which data of the scalable encoded data corresponds to the different compression rates. Combined data comprising the scalable encoded data and the compression factor indicators are stored in a frame memory (105). An application having a given compression factor requirement may use the compression factor indicators to access the scalable encoded data of the frame memory (105) which is required for processing. A plurality of applications may access the same frame memory (105) thereby allowing for scalable encoded data which can be used with a plurality of applications having different compression factor requirements.

摘要翻译： 本发明涉及内容信号处理，特别涉及视频内容信号的处理。 用于内容信号处理的装置（100）包括可缩放编码器（101），用于对内容信号进行编码以产生包括与多个压缩率相关联的数据的可分级编码数据。 压缩处理器（105）确定指示与多个压缩率相关联的数据的压缩因子指示符。 因此，压缩因子指示符指示可缩放编码数据的哪个数据对应于不同的压缩率。 包括可缩放编码数据和压缩因子指示符的组合数据被存储在帧存储器（105）中。 具有给定压缩因子要求的应用可以使用压缩因子指示符来访问处理所需的帧存储器（105）的可缩放编码数据。 多个应用可以访问相同的帧存储器（105），从而允许可以与具有不同压缩因子要求的多个应用使用的可缩放编码数据。

公开(公告)号：US20070008342A1

公开(公告)日：2007-01-11

申请号：US10554385

申请日：2004-04-27

申请人： Ramanathan Sethuraman ,  Christiaan Varekamp ,  Fabian Ernst

发明人： Ramanathan Sethuraman ,  Christiaan Varekamp ,  Fabian Ernst

IPC分类号： G09G5/00

CPC分类号： H04N19/85 ,  G06T7/11 ,  G06T2207/10016 ,  G06T2207/20021

摘要： A method of converting of a first set (100a) of initial segments of an image into a second set of updated segments (A′,B′,C′,D′) is disclosed. The method comprises iterative updates of intermediate segments (A,B,C,D) being derived from respective initial segments. Each update comprises determining whether a pixel (300) should be moved from a first intermediate segment (A) to a second intermediate segment (B), on basis of a pixel value of the pixel, on basis of a first parameter of the intermediate segment (A) and on basis of a second parameter of the second intermediate segment (B). The iterative updates are performed on block base. That means that first a number of iterative updates are performed for pixels of a first two-dimensional block of pixels (200) of the image and after that the number of iterative updates are performed for pixels of a second two-dimensional block of pixels (204) of the image.

摘要翻译： 公开了一种将图像的初始段的第一组（100a）转换为第二组更新段（A'，B'，C'，D'）的方法。 该方法包括从相应的初始段导出的中间段（A，B，C，D）的迭代更新。 每个更新包括基于中间片段的第一参数来确定像素（300）是否应当从第一中间片段（A）移动到第二中间片段（B），基于像素的像素值 （A）并且基于第二中间段（B）的第二参数。 迭代更新以块为基础进行。 这意味着首先对图像的第一二维像素块（200）的像素执行多次迭代更新，然后针对第二二维像素块的像素执行迭代更新次数（ 204）的图像。