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    Data processing apparatus with parallel operating functional units
    1.
    发明授权
    Data processing apparatus with parallel operating functional units 有权
    具有并行运行功能单元的数据处理装置

    公开(公告)号：US07664929B2

    公开(公告)日：2010-02-16

    申请号：US10530375

    申请日：2003-09-17

    申请人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman ,  Srinivasan Balakrishnan ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

    发明人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman ,  Srinivasan Balakrishnan ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3802 ,  G06F9/3853

    摘要： A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

    摘要翻译： 用VLIW数据处理装置执行指令字的程序。 该装置包括能够并行地从每个指令字执行多个指令的多个功能单元。 来自各个指令字中的至少一些的指令被并行地从相应的存储器单元中取出，用功能单元共用的指令地址寻址。 将指令地址转换为物理地址可以针对一个或多个特定存储器单元进行修改。 修改由程序中的修改更新指令控制。 因此，可以根据程序执行来选择来自存储器单元的指令将响应于指令地址而组合到指令字中。

    Data processing apparatus address range dependent parallelization of instructions
    2.
    发明授权
    Data processing apparatus address range dependent parallelization of instructions 有权
    数据处理装置地址范围依赖于指令的并行化

    公开(公告)号：US08364935B2

    公开(公告)日：2013-01-29

    申请号：US10530495

    申请日：2003-10-01

    申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

    发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

    摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

    摘要翻译： 数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。 指令执行单元，并行地从指令字处理多个指令。 检测单元，检测指示地址所在的多个范围中的哪一个。 检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。 在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。

    Data processing apparatus with parallel operating functional units
    4.
    发明申请
    Data processing apparatus with parallel operating functional units 有权
    具有并行运行功能单元的数据处理装置

    公开(公告)号：US20050273569A1

    公开(公告)日：2005-12-08

    申请号：US10530375

    申请日：2003-09-17

    申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

    发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/00

    CPC分类号： G06F9/3802 ,  G06F9/3853

    摘要： A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

    摘要翻译： 用VLIW数据处理装置执行指令字的程序。 该装置包括能够并行地从每个指令字执行多个指令的多个功能单元。 来自各个指令字中的至少一些的指令被并行地从相应的存储器单元中取出，用功能单元共用的指令地址寻址。 将指令地址转换为物理地址可以针对一个或多个特定存储器单元进行修改。 修改由程序中的修改更新指令控制。 因此，可以根据程序执行来选择来自存储器单元的指令将响应于指令地址而组合到指令字中。

    Segment-based motion estimation
    5.
    发明申请
    Segment-based motion estimation 审中-公开
    基于段的运动估计

    公开(公告)号：US20060098737A1

    公开(公告)日：2006-05-11

    申请号：US10539898

    申请日：2003-11-20

    申请人： Ramanathan Sethuraman ,  Fabian Ernst ,  Patrick Meuwissen ,  Harm Johannes Antonius Peters ,  Rafael Peset Llopis

    发明人： Ramanathan Sethuraman ,  Fabian Ernst ,  Patrick Meuwissen ,  Harm Johannes Antonius Peters ,  Rafael Peset Llopis

    IPC分类号： H04N11/02 ,  H04N7/12 ,  H04B1/66 ,  H04N11/04

    CPC分类号： G06T7/20 ,  G06T7/223 ,  H04N19/20 ,  H04N19/51

    摘要： A method to determine motion vectors for respective segments (S11-S14) of a segmented image (100) comprises: creating sets of candidate motion vectors for the respective segments (S11-S14); dividing the segmented image (100) into a grid of blocks (b11-b88) of pixels; determining for the blocks (b11-b88) of pixels which of the candidate motion vectors belong to the blocks (b11-b88), on basis of the segments (S11-S14) and the locations of the blocks (b11-b88) within the segmented image (100); computing partial match errors for the blocks (b11-b88) on basis of the determined candidate motion vectors and on basis of pixel values of a further image (102); combining the partial match errors into a number of match errors per segment; selecting for each of the sets of candidate motion vectors respective candidate motion vectors on basis of the match errors; and assigning the selected candidate motion vectors as the motion vectors for the respective segments (S11-S14).

    摘要翻译： 确定分割图像（100）的各个段（S 11 -S 14）的运动矢量的方法包括：为各个段创建候选运动矢量集合（S 11 -S 14）; 将分割图像（100）划分成像素的块（b 11 -b 88）的网格; 基于片段（S 11 -S 14）和块的位置（S 11 -S 14），确定候选运动矢量中属于块（b 11 -b 88）的像素的块（b 11 -b88） b 11 -b 88）; 基于所确定的候选运动矢量和基于另一图像（102）的像素值来计算块（b 11 -b 88）的部分匹配误差; 将部分匹配错误组合成每个段的多个匹配错误; 基于匹配误差来选择候选运动矢量各个候选运动矢量中的每一组; 并且将所选择的候选运动矢量分配为各个段的运动矢量（S 11 -S 14）。

    Vl1w processor with power saving
    7.
    发明申请
    Vl1w processor with power saving 有权
    Vl1w处理器省电

    公开(公告)号：US20060156004A1

    公开(公告)日：2006-07-13

    申请号：US10530639

    申请日：2003-09-17

    申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

    发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

    IPC分类号： H04N17/00

    CPC分类号： G06F9/3853 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30167 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

    摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.

    摘要翻译： 数据处理装置具有指令存储器系统，其被布置为输出能够包含多个指令的指令字，响应于相应的指令地址输出相应的指令字。 指令执行单元包含多个功能单元，每个功能单元能够执行来自指令字的相应指令，并且与其他功能单元从指令字执行其他指令并行执行。 提供省电电路以将功能单元和/或指令存储器的可选择子集切换到省电状态，而指令存储器的其他功能单元和部分在正常功耗状态下继续处理指令。 省电电路根据程序执行选择指令存储器的功能单元和/或部分。

    Compression
    8.
    发明授权
    Compression 失效
    压缩

    公开(公告)号：US07085321B2

    公开(公告)日：2006-08-01

    申请号：US10280649

    申请日：2002-10-25

    申请人： Rafael Peset Llopis

    发明人： Rafael Peset Llopis

    IPC分类号： H04N7/12

    CPC分类号： H04N19/428 ,  H04N19/30

    摘要： The invention relates to a method of controlling decoder drift for memory compression comprising the steps of providing a decoded bit-stream output of a decoder (79) and a bit-stream input to an encoder (76) in a first pass of a coding loop, where the bit-stream input to the encoder (76) is based on the decoded bit-stream output of the decoder (79), determining a difference between the bit-stream input to the encoder (76) and the decoded bit-stream output of the decoder (79), where the difference is due to a compression of the decoded bit-stream output of the decoder (79) in the encoder (76) during the first coding loop and correcting the decoded bit-stream output of the decoder (79) in dependence on the determined difference in a second pass of the coding loop.

    摘要翻译： 本发明涉及一种控制用于存储器压缩的解码器漂移的方法，包括以下步骤：在编码环路的第一遍中提供解码器（79）的解码比特流输出和比特流输入到编码器（76） ，其中输入到编码器（76）的比特流基于解码器（79）的解码比特流输出，确定到编码器（76）的比特流输入与解码比特流之间的差异 解码器（79）的输出，其中差异是由于在第一编码循环期间编码器（76）中的解码器（79）的解码比特流输出的压缩，并且校正了解码器（79）的解码比特流输出 解码器（79），其取决于所确定的编码环路的第二遍中的差。

    Packing and unpacking for variable number of bits
    9.
    发明申请
    Packing and unpacking for variable number of bits 审中-公开
    包装和拆包可变位数

    公开(公告)号：US20050174268A1

    公开(公告)日：2005-08-11

    申请号：US10515454

    申请日：2003-04-29

    申请人： Rafael Peset Llopis

    发明人： Rafael Peset Llopis

    IPC分类号： H03M7/40 ,  G06F5/00 ,  G06F7/76 ,  H03M7/00

    CPC分类号： G06F7/76 ,  G06F5/00

    摘要： A method of packing a variable number of bits from an input bit stream into an output bit stream, comprising the steps of: defining a maximum number n of bits which are to be packed into the output bit stream within a clock cycle, providing a validation bit stream which defines positions of those bits in said input bit stream as output bits which are to be selected for packing; selecting the output bits and adding only the output bits to said output bit stream.

    摘要翻译： 一种从输入比特流将可变数目的比特数据包打包成输出比特流的方法，包括以下步骤：在时钟周期内定义要打包到输出比特流中的比特数的最大数量n，提供验证 位流，其将所述输入位流中的这些位的位置定义为要被选择用于打包的输出位; 选择输出位并仅将输出位加到所述输出位流。

    Electronic circuit with dual edge triggered flip-flop
    10.
    发明授权
    Electronic circuit with dual edge triggered flip-flop 失效
    具有双边沿触发触发器的电子电路

    公开(公告)号：US6137331A

    公开(公告)日：2000-10-24

    申请号：US184533

    申请日：1998-11-02

    申请人： Rafael Peset Llopis

    发明人： Rafael Peset Llopis

    IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/12 ,  H03K3/286 ,  H03K3/356

    CPC分类号： H03K3/012 ,  H03K3/037

    摘要： The electronic circuit contains dual edge triggered flip-flop, which loads data on both the rising edge and the falling edge of a clock signal. The clock signal is supplied by a clock supply circuit with an enable input and a source input for receiving a source signal. The clock supply circuit toggles the clock signal as from an earliest available edge of the source signal after the enable signal at the enable input switches to an active state, irrespective of a polarity of said earliest available edge.

    摘要翻译： 电子电路包含双边沿触发触发器，它在时钟信号的上升沿和下降沿都加载数据。 时钟信号由具有用于接收源信号的使能输入和源极输入的时钟供应电路提供。 在使能输入的使能信号切换到有效状态之后，与所述最早可用边沿的极性无关地，时钟供应电路切换来自源信号的最早可用边沿的时钟信号。