公开(公告)号：US20060017052A1

公开(公告)日：2006-01-26

申请号：US11083225

申请日：2005-03-18

Applicant: Ramesh Kakkad

Inventor： Ramesh Kakkad

IPC: H01L29/786 ,  H01L21/84

CPC classification number: H01L21/02686 ,  H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/84 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

Abstract: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; partially crystallizing the amorphous silicon by applying an annealing process to the silicon layer under an atmosphere of H2O at a predetermined temperature; forming a polycrystalline silicon layer by applying an laser annealing process to the partially crystallized amorphous silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; and forming a gate electrode on the gate insulating layer, so that a substrate is prevented from being bent due to high temperature crystallization while the amorphous silicon is crystallized through an SPC process, thereby reducing defects of the thin film transistor.

Abstract translation: 提供了半导体器件及其制造方法。 该方法包括：在衬底上沉积含有非晶硅的硅层; 通过在H 2 O 2气氛下在预定温度下对硅层施加退火工艺来部分地使非晶硅结晶; 通过对所述部分结晶的非晶硅层施加激光退火工艺来形成多晶硅层; 在所述多晶硅层上形成栅极绝缘层; 以及在栅极绝缘层上形成栅电极，从而防止由于高温结晶而使衬底弯曲，而非晶硅通过SPC工艺结晶化，从而减少了薄膜晶体管的缺陷。

公开(公告)号：US07943447B2

公开(公告)日：2011-05-17

申请号：US12184525

申请日：2008-08-01

Applicant: Ramesh Kakkad

Inventor： Ramesh Kakkad

IPC: H01L21/00

CPC classification number: H01L29/66765 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757

Abstract: The present invention includes methods to crystallize amorphous silicon. A structure including a conductive film with at least one conductive layer in thermal contact with an amorphous silicon (a-Si) layer to be crystallized is exposed to an alternating or varying magnetic field. The conductive film is more easily heated by the alternative or varying magnetic field, which, in-turn, heats the a-Si film and crystallizes it while keeping the substrate at a low enough temperature to avoid damage to or bending of the substrate. The method can be applied to the fabrication of many semiconductor devices, including thin film transistors and solar cells.

Abstract translation: 本发明包括使非晶硅结晶的方法。 包括具有与待结晶的非晶硅（a-Si）层热接触的至少一个导电层的导电膜的结构暴露于交替或变化的磁场。 导电膜更容易被替代或变化的磁场加热，这又反过来加热a-Si膜并使其结晶，同时保持基板在足够低的温度下，以避免基板的损坏或弯曲。 该方法可以应用于许多半导体器件的制造，包括薄膜晶体管和太阳能电池。

公开(公告)号：US20070004185A1

公开(公告)日：2007-01-04

申请号：US11425268

申请日：2006-06-20

Applicant: Ramesh Kakkad

Inventor： Ramesh Kakkad

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L27/1296 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02672 ,  H01L27/1281 ,  H01L29/66765

Abstract: A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly reduced. First, a composite layer structure consisting of an undoped (or a lightly doped) a-Si layer and a heavily doped (either p-type or n-type) a-Si layer is formed and it is subsequently annealed at an elevated temperature. The solid phase crystallization starts from the heavily doped amorphous silicon layer at a substantially reduced thermal budget and proceeds to crystallize the undoped amorphous silicon layer in contact with the heavily doped film at reduced thermal budget. The method can be applied to form poly silicon thin film transistor at reduced thermal budgets.

Abstract translation: 用于结晶未掺杂（或轻掺杂）非晶Si（a-Si）的固相结晶（SPC）热预算的方法显着降低。 首先，形成由未掺杂（或轻掺杂）a-Si层和重掺杂（p型或n型）a-Si层组成的复合层结构，随后在升高的温度下退火。 固相结晶以大大降低的热预算从重掺杂的非晶硅层开始，并且在降低的热预算下进行结晶与重掺杂膜接触的未掺杂的非晶硅层。 该方法可以应用于以较低的热预算形成多晶硅薄膜晶体管。

公开(公告)号：US06239451B1

公开(公告)日：2001-05-29

申请号：US09447756

申请日：1999-11-23

Applicant: Stephen J. Fonash ,  Ramesh Kakkad

Inventor： Stephen J. Fonash ,  Ramesh Kakkad

IPC: H01L2904

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L31/03682 ,  H01L31/1864 ,  Y02E10/546 ,  Y02P70/521

Abstract: An ultra-thin highly electrically conductive material is prepared by depositing an amorphous material, substantially free of crystal growth-inducing nuclei and sites, onto a substrate. Deposition is preferably with a plasma deposition reactor, with semiconductor dopants introduced during deposition. Deposition time is preferably adjusted to create an amorphous film of a desired thickness, e.g., 200 Å. After deposition, the amorphous film is annealed preferably with a rapid thermal annealing process for four minutes at 700° C. The annealing triggers the creation of nuclei and subsequent large grain growth in the film, releases energy contained within the amorphous material, and helps drive crystallization and dopant activation. After annealing the material is completely crystallized, and contains large grains whose lateral dimensions can exceed the film thickness by a factor of fifty. Because the grain structure is large there are few grain boundaries to absorb dopants and carriers, and thus degrade electrical conductivity. Thin film material produced according to the present invention can exhibit conductivity 1010 times better than prior art materials at 200 Å thickness. Such material is highly suitable in thin film semiconductor structures including buried gate memory devices, shallow emitter devices, as well as photovoltaic cells, X-ray and other radiation detectors. The disclosed annealing process will substantially improve conductivity of amorphous thin film materials, even if such materials are produced by methods other than deposition.

Abstract translation: 通过将基本上不含结晶生长诱导核和位点的无定形材料沉积到基底上来制备超薄高导电性材料。 沉积优选用等离子体沉积反应器，在沉积期间引入半导体掺杂剂。 优选调节沉积时间以产生所需厚度例如200的非晶膜。 沉积后，非晶膜优选在700℃下用快速热退火工艺退火四分钟。退火触发了膜的产生和随后的大晶粒生长，释放非晶态材料中所含的能量，并且有助于驱动 结晶和掺杂剂活化。 退火之后，材料完全结晶，并且包含大的晶粒，其横向尺寸可以超过膜厚度五十倍。 由于晶粒结构大，因此难以吸收掺杂剂和载流子的晶界，导致导电性降低。 根据本发明生产的薄膜材料可以表现出比现有技术材料厚200埃的导电率1010倍。 这种材料非常适用于包括掩埋栅极存储器件，浅发射器件以及光伏电池，X射线和其它辐射探测器的薄膜半导体结构。 所公开的退火工艺将显着改善非晶薄膜材料的导电性，即使这些材料是通过沉积以外的方法生产的。

公开(公告)号：US08294840B2

公开(公告)日：2012-10-23

申请号：US12051006

申请日：2008-03-19

Applicant: Ramesh Kakkad ,  Chieh-Wen Lin

Inventor： Ramesh Kakkad ,  Chieh-Wen Lin

IPC: G02F1/136 ,  G02F1/1343

CPC classification number: G02F1/134363 ,  G02F1/13454 ,  G02F1/13624 ,  G02F2001/134372 ,  G02F2201/40

Abstract: A system for displaying images, having a display panel, comprising: a lower substrate with a first surface, wherein the first surface is divided into a pixel area and a driver area; a peripheral circuit within the driver area on the first surface; at least one thin film transistor is formed in the pixel area, wherein the thin film transistor comprises an active layer, a gate dielectric layer overlying the active layer, and a gate electrode overlying the gate dielectric layer, and the active layer has source and drain regions; a first transparent electrode layer directly overlapped on a portion of the drain region, electrically connected thereto; and a second transparent electrode pattern is disposed on the gate dielectric layer, opposing the first transparent electrode layer.

Abstract translation: 一种用于显示具有显示面板的图像的系统，包括：具有第一表面的下基板，其中所述第一表面被划分为像素区域和驱动器区域; 在第一表面上的驱动器区域内的外围电路; 在所述像素区域中形成至少一个薄膜晶体管，其中所述薄膜晶体管包括有源层，覆盖所述有源层的栅极电介质层和覆盖所述栅极介电层的栅电极，并且所述有源层具有源极和漏极 区域; 直接重叠在所述漏极区域的与其电连接的第一透明电极层; 并且第二透明电极图案设置在栅电介质层上，与第一透明电极层相对。

公开(公告)号：US07670886B2

公开(公告)日：2010-03-02

申请号：US11472858

申请日：2006-06-22

Applicant: Ramesh Kakkad

Inventor： Ramesh Kakkad

IPC: H01L21/00

CPC classification number: H01L21/02675 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/02686 ,  H01L21/2026 ,  H01L27/1285 ,  H01L29/66757

Abstract: A method of fabricating a polysilicon film includes: forming a seed layer on a surface of a substrate; forming a silicon layer over the surface of the seed layer; and performing a laser annealing process to transform the silicon layer into a polysilicon layer at a laser energy equal to or greater than that needed to cause complete melting of the silicon layer.

Abstract translation: 制造多晶硅膜的方法包括：在基板的表面上形成种子层; 在种子层的表面上形成硅层; 以及进行激光退火处理，以等于或大于使硅层完全熔化所需的激光能量将硅层转化为多晶硅层。

公开(公告)号：US6013565A

公开(公告)日：2000-01-11

申请号：US290227

申请日：1994-08-15

Applicant: Stephen J. Fonash ,  Ramesh Kakkad

Inventor： Stephen J. Fonash ,  Ramesh Kakkad

IPC: H01L21/20 ,  H01L31/0368 ,  H01L31/18 ,  H01L21/02

CPC classification number: H01L21/2022 ,  H01L31/03682 ,  H01L31/1864 ,  Y02E10/546 ,  Y02P70/521

Abstract: An ultra-thin highly electrically conductive material is prepared by depositing an amorphous material, substantially free of crystal growth-inducing nuclei and sites, onto a substrate. Deposition is preferably with a plasma deposition reactor, with semiconductor dopants introduced during deposition. Deposition time is preferably adjusted to create an amorphous film of a desired thickness, e.g., 200 .ANG.. After deposition, the amorphous film is annealed preferably with a rapid thermal annealing process for four minutes at 700.degree. C. The annealing triggers the creation of nuclei and subsequent large grain growth in the film, releases energy contained within the amorphous material, and helps drive crystallization and dopant activation. After annealing the material is completely crystallized, and contains large grains whose lateral dimensions can exceed the film thickness by a factor of fifty. Because the grain structure is large there are few grain boundaries to absorb dopants and carriers, and thus degrade electrical conductivity. Thin film material produced according to the present invention can exhibit conductivity 10.sup.10 times better than prior art materials at 200 .ANG. thickness. Such material is highly suitable in thin film semiconductor structures including buried gate memory devices, shallow emitter devices, as well as photovoltaic cells, X-ray and other radiation detectors. The disclosed annealing process will substantially improve conductivity of amorphous thin film materials, even if such materials are produced by methods other than deposition.

Abstract translation: 通过将基本上不含结晶生长诱导核和位点的无定形材料沉积到基底上来制备超薄高导电性材料。 沉积优选用等离子体沉积反应器，在沉积期间引入半导体掺杂剂。 优选调节沉积时间以产生所需厚度的无定形膜，例如200安培。 沉积后，非晶膜优选在700℃下快速热退火4分钟进行退火。退火触发了膜的产生和随后的大晶粒生长，释放出无定形材料内的能量，并且有助于驱动 结晶和掺杂剂活化。 退火之后，材料完全结晶，并且包含大的晶粒，其横向尺寸可以超过膜厚度五十倍。 由于晶粒结构大，因此难以吸收掺杂剂和载流子的晶界，导致导电性降低。 根据本发明生产的薄膜材料的电导率可以比现有技术的材料在200厚度下显示出1010倍。 这种材料非常适用于包括掩埋栅极存储器件，浅发射器件以及光伏电池，X射线和其它辐射探测器的薄膜半导体结构。 所公开的退火工艺将显着改善非晶薄膜材料的导电性，即使这些材料是通过沉积以外的方法生产的。

公开(公告)号：US08045082B2

公开(公告)日：2011-10-25

申请号：US12052197

申请日：2008-03-20

Applicant: Ramesh Kakkad ,  Hsiao-Wei Kao ,  Chung-Sheng Lin ,  Chih-Chung Liu

Inventor： Ramesh Kakkad ,  Hsiao-Wei Kao ,  Chung-Sheng Lin ,  Chih-Chung Liu

IPC: G02F1/136

CPC classification number: H01L29/4908 ,  H01L27/1255

Abstract: A system for display images comprising a thin film transistor array substrate is disclosed. The system for display images comprises a substrate having a pixel area, a source/drain region overlying the substrate within an active layer in the pixel area, a bottom electrode overlying the substrate in the pixel area, a top electrode overlying the bottom electrode, a first dielectric layer disposed on the active layer, a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the bottom electrode and the top electrode and a gate disposed overlying the active layer, wherein the first and second dielectric layers are interposed between the gate and the active layer.

Abstract translation: 公开了一种包括薄膜晶体管阵列基板的显示图像系统。 用于显示图像的系统包括具有像素区域的衬底，覆盖像素区域中的有源层中的衬底的源极/漏极区域，在像素区域中覆盖衬底的底部电极，覆盖底部电极的顶部电极， 设置在有源层上的第一电介质层，设置在第一电介质层上的第二电介质层，其中第二电介质层设置在底电极和顶电极之间，栅极设置在有源层上，其中第一和第二电介质 层插入在栅极和有源层之间。

公开(公告)号：US20090278121A1

公开(公告)日：2009-11-12

申请号：US12427142

申请日：2009-04-21

Applicant: Ramesh Kakkad ,  Keiichi Sano ,  Fu-Yuan Hsueh ,  Chih-Chung Liu ,  Sheng-Wen Chang

Inventor： Ramesh Kakkad ,  Keiichi Sano ,  Fu-Yuan Hsueh ,  Chih-Chung Liu ,  Sheng-Wen Chang

IPC: H01L33/00 ,  H01L31/0376 ,  H01L29/786

CPC classification number: H01L31/147 ,  G02F1/13318 ,  G02F1/1362 ,  G02F2001/13324 ,  G02F2201/58 ,  H01L31/022466 ,  H01L31/035281 ,  H01L31/03682 ,  H01L31/03762 ,  H01L31/1055 ,  H01L31/1884 ,  H01L31/202 ,  Y02E10/50 ,  Y02P70/521

Abstract: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.

Abstract translation: 用于显示图像的系统包括薄膜晶体管阵列基板，其包括具有薄膜晶体管阵列的基板和至少一个含有形成在该基板上的非晶硅层的光感测元件，其中该光感测元件具有垂直的电流流动方向 到基底。

公开(公告)号：US07507648B2

公开(公告)日：2009-03-24

申请号：US11425268

申请日：2006-06-20

Applicant: Ramesh Kakkad

Inventor： Ramesh Kakkad

IPC: H01L21/00

CPC classification number: H01L27/1296 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02672 ,  H01L27/1281 ,  H01L29/66765

Abstract: A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly reduced. First, a composite layer structure consisting of an undoped (or a lightly doped) a-Si layer and a heavily doped (either p-type or n-type) a-Si layer is formed and it is subsequently annealed at an elevated temperature. The solid phase crystallization starts from the heavily doped amorphous silicon layer at a substantially reduced thermal budget and proceeds to crystallize the undoped amorphous silicon layer in contact with the heavily doped film at reduced thermal budget. The method can be applied to form poly silicon thin film transistor at reduced thermal budgets.

Abstract translation: 用于结晶未掺杂（或轻掺杂）非晶Si（a-Si）的固相结晶（SPC）热预算的方法显着降低。 首先，形成由未掺杂（或轻掺杂）a-Si层和重掺杂（p型或n型）a-Si层组成的复合层结构，随后在升高的温度下退火。 固相结晶以大大降低的热预算从重掺杂的非晶硅层开始，并且在降低的热预算下进行结晶与重掺杂膜接触的未掺杂的非晶硅层。 该方法可以应用于以较低的热预算形成多晶硅薄膜晶体管。