公开(公告)号：US08468271B1

公开(公告)日：2013-06-18

申请号：US12698826

申请日：2010-02-02

申请人： Ramesh Panwar ,  David Weinberg

发明人： Ramesh Panwar ,  David Weinberg

IPC分类号： G06F15/16

CPC分类号： G06Q30/0615

摘要： In general, techniques are described for utilizing anonymous cookies within computer networks to protect customer identities. In particular, a network device is configured to communicate with an edge router of a service provider network that provides access to a public network having network destinations. The network device includes a control unit and an interface. The control unit executes a content delivery layer and a privacy services layer. The content delivery layer receives a network communication sent from one of the customer devices to the public network. The privacy services layer replaces a destination-specified cookie within the network communication with an anonymous cookie, each of which conform to an application layer protocol. The anonymous cookie also specifies a pseudonym for the one of the customer devices that originated the network communication. The at least one interface then forwards the network communication including the anonymous cookie to the network destination.

摘要翻译： 一般来说，描述了利用计算机网络中的匿名cookie来保护客户身份的技术。 特别地，网络设备被配置为与提供对具有网络目的地的公共网络的访问的服务提供商网络的边缘路由器进行通信。 网络设备包括控制单元和接口。 控制单元执行内容传送层和隐私服务层。 内容传送层接收从一个客户设备发送到公共网络的网络通信。 隐私服务层将网络通信中的目的地指定的cookie替换为匿名cookie，每个Cookie符合应用层协议。 匿名cookie还为发起网络通信的客户设备之一指定了一个假名。 至少一个接口然后将包括匿名cookie的网络通信转发到网络目的地。

公开(公告)号：US20100080224A1

公开(公告)日：2010-04-01

申请号：US12242172

申请日：2008-09-30

申请人： Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan ,  Jean-Marc Frailong

发明人： Ramesh Panwar ,  Deepak Goel ,  Srinivasan Jagannadhan ,  Jean-Marc Frailong

IPC分类号： H04L12/56

CPC分类号： H04L45/745 ,  H04L49/1515 ,  H04L49/503 ,  H04L69/22

摘要： In one embodiment, a method, comprising producing a first policy vector based on a first portion of a data packet received at a multi-stage switch. The method also includes producing a second policy vector based on a second portion of the data packet different than the first portion of the data packet. A third policy vector is produced based on a combination of at least the first policy vector and at least the second policy vector. The third policy vector including a combination of bit values configured to trigger an element at the multi-stage switch to process the data packet.

摘要翻译： 在一个实施例中，一种方法，包括基于在多级交换机处接收到的数据分组的第一部分产生第一策略向量。 该方法还包括基于不同于数据分组的第一部分的数据分组的第二部分产生第二策略向量。 基于至少第一策略向量和至少第二策略向量的组合来生成第三策略向量。 第三策略向量包括被配置为触发多级切换处的元素以处理数据分组的比特值的组合。

公开(公告)号：US20060107055A1

公开(公告)日：2006-05-18

申请号：US10990945

申请日：2004-11-17

申请人： Ramesh Panwar ,  Joseph Tardo ,  Manish Kadam ,  Swati Deshpande ,  Sunil Aurora

发明人： Ramesh Panwar ,  Joseph Tardo ,  Manish Kadam ,  Swati Deshpande ,  Sunil Aurora

IPC分类号： H04L9/00

CPC分类号： H04L63/1441 ,  G06F21/564

摘要： A method and system for detecting a pattern derived from or related to a data signature in data packets is provided. An intrusion detection module accepts a data packet and compares all or portions of the data packet with a set of data patterns. One or more data patterns may be related to, or indicate the existence of, or derived from a virus or other data structure, software code, software program, portions of content of a data packet, a universal resource locater, and/or a traffic classification indicator.

摘要翻译： 提供了一种用于检测从数据分组中的数据签名导出或相关的模式的方法和系统。 入侵检测模块接受数据包，并将数据包的全部或部分与一组数据模式进行比较。 一个或多个数据模式可以与病毒或其他数据结构有关，或指示病毒或其他数据结构的存在或衍生，软件代码，软件程序，数据分组的内容部分，通用资源定位符和/或流量 分类指标。

公开(公告)号：US06898673B2

公开(公告)日：2005-05-24

申请号：US10105973

申请日：2002-03-25

申请人： Frederick Gruner ,  Robert Hathaway ,  Ramesh Panwar ,  Elango Ganesan ,  Nazar Zaidi

发明人： Frederick Gruner ,  Robert Hathaway ,  Ramesh Panwar ,  Elango Ganesan ,  Nazar Zaidi

IPC分类号： G06F12/00 ,  G06F12/08 ,  H04L12/56 ,  G06F13/00

CPC分类号： H04L47/10 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  H04L47/12 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/765 ,  H04L47/805 ,  H04L47/822

摘要： A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a media access controller engine and a data transfer engine. The media access controller engine couples the compute engine to a communications network. The data transfer engine couples the media access controller engine to a set of cache memory. In further embodiments, a compute engine includes two media access controller engines. A reception media access controller engine receives data from the communications network. A transmission media access controller engine transmits data to the communications network. The compute engine also includes two data transfer engines. A streaming output engine stores network data from the reception media access controller engine in cache memory. A streaming input engine transfers data from cache memory to the transmission media access controller engine. In one implementation, the compute engine performs different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

摘要翻译： 计算引擎包括耦合到协处理器的中央处理单元。 协处理器包括媒体访问控制器引擎和数据传输引擎。 媒体访问控制器引擎将计算引擎耦合到通信网络。 数据传输引擎将媒体访问控制器引擎耦合到一组高速缓冲存储器。 在另外的实施例中，计算引擎包括两个媒体访问控制器引擎。 接收媒体接入控制器引擎从通信网络接收数据。 传输媒体接入控制器引擎向通信网络发送数据。 计算引擎还包括两个数据传输引擎。 流输出引擎将来自接收媒体访问控制器引擎的网络数据存储在高速缓冲存储器中。 流输入引擎将数据从高速缓冲存储器传输到传输介质访问控制器引擎。 在一个实现中，计算引擎执行不同的网络服务，包括但不限于：1）虚拟专用网; 2）安全套接字层处理; 3）网页缓存; 4）超文本标记语言压缩; 5）病毒检查; 6）防火墙支持; 和7）网页切换。

公开(公告)号：US06892282B2

公开(公告)日：2005-05-10

申请号：US10105993

申请日：2002-03-25

申请人： David Hass ,  Mark Vilas ,  Frederick Gruner ,  Ramesh Panwar ,  Nazar Zaidi

发明人： David Hass ,  Mark Vilas ,  Frederick Gruner ,  Ramesh Panwar ,  Nazar Zaidi

IPC分类号： G06F12/00 ,  G06F12/08 ,  H04L12/56 ,  G06F13/00

CPC分类号： H04L47/10 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  H04L47/12 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/765 ,  H04L47/805 ,  H04L47/822

摘要： A multi-processor unit includes a set of processing clusters. Each processing cluster is coupled to a data ring and a snoop ring. The unit also includes a snoop controller adapted to process memory requests from each processing cluster. The data ring enables clusters to exchange requested information. The snoop ring is coupled to the snoop controller—enabling the snoop controller to forward each cluster's memory requests to the other clusters in the form of snoop requests.

摘要翻译： 多处理器单元包括一组处理集群。 每个处理集群耦合到数据环和监听环。 该单元还包括适于处理来自每个处理簇的存储器请求的窥探控制器。 数据环使群集能够交换请求的信息。 侦听环与侦听控制器相连，使窥探控制器能够以窥探请求的形式将每个群集的内存请求转发给其他群集。

公开(公告)号：US06880049B2

公开(公告)日：2005-04-12

申请号：US10105924

申请日：2002-03-25

申请人： Fred Gruner ,  David Hass ,  Ramesh Panwar ,  Nazar Zaidi

发明人： Fred Gruner ,  David Hass ,  Ramesh Panwar ,  Nazar Zaidi

IPC分类号： G06F12/00 ,  G06F12/08 ,  H04L12/56 ,  G06F13/00

CPC分类号： H04L47/10 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  H04L47/12 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/765 ,  H04L47/805 ,  H04L47/822

摘要： A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in the set of first tier cache memory. The second tier cache memory includes a data ring interface and a snoop ring interface.

摘要翻译： 一组缓存存储器包括一组第一层高速缓冲存储器和第二层缓存存储器。 在第一层高速缓冲存储器集合中，每一个第一级缓存存储器耦合到一组计算引擎中的计算引擎。 第二层缓存存储器耦合到第一层高速缓冲存储器集合中的每个第一层高速缓存存储器。 第二层缓存包括数据环接口和窥探环接口。

公开(公告)号：US6085305A

公开(公告)日：2000-07-04

申请号：US881729

申请日：1997-06-25

申请人： Ramesh Panwar ,  Arjun Prabhu

发明人： Ramesh Panwar ,  Arjun Prabhu

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F15/82

CPC分类号： G06F9/30094 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857

摘要： A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

摘要翻译： 一种处理器，包括产生无序结果和无序条件代码的至少一个执行单元。 通过提供具有多个时隙的结果缓冲器并提供具有与结果缓冲器相同数量的时隙的条件代码缓冲器来维持处理器的精确架构状态，条件代码缓冲器中的每个时隙与一个对应于 结果缓冲区中的一个插槽。 处理器中的每个实时指令都在结果缓冲区和条件代码缓冲区中分配一个时隙。 由执行单元产生的每个推测结果都存储在结果缓冲区中的分配时隙中。 当指令退出时，该指令的结果被传送到架构结果寄存器，并且由该指令生成的任何条件代码被传送到架构条件代码寄存器。

公开(公告)号：US6058472A

公开(公告)日：2000-05-02

申请号：US882311

申请日：1997-06-25

申请人： Ramesh Panwar ,  P.K. Chidambaran ,  Ricky C. Hetherington

发明人： Ramesh Panwar ,  P.K. Chidambaran ,  Ricky C. Hetherington

IPC分类号： G06F9/38

CPC分类号： G06F9/3834 ,  G06F9/3861

摘要： A system, apparatus and method for ensuring program correctness in an out-of-order processor spite of younger load instructions being boosted past an older store utilizing a memory disambiguation buffer ("MDB"). The memory disambiguation buffer stores all memory operations that have not yet been retired. Each entry has several fields amongst which are the data and the addresses of the memory operations. An incoming load checks its address against the addresses of all the stores. If there is a match against an older store, then the load must have received old data from the data cache and the load operation is replayed to seek data from the memory disambiguation buffer on the replay. If on the other hand, there were no matches on any older store, the load is assumed to have received the right data from the data cache (assuming a data cache hit). An incoming store checks its address against the addresses of all younger loads. If there is a match against any younger load, then the younger load is replayed along with all of its dependents.

摘要翻译： 一种用于确保无序处理器中的程序正确性的系统，装置和方法，尽管较小的加载指令通过使用存储器消歧缓冲器（“MDB”）的较旧存储器被提升。 内存消歧缓冲区存储所有尚未被停用的内存操作。 每个条目都有几个字段，其中包括数据和内存操作的地址。 传入的负载根据所有商店的地址检查其地址。 如果与较旧的存储器进行匹配，则加载必须已经从数据高速缓存中接收到旧数据，并且重播加载操作以从重放的内存消歧缓冲区中寻找数据。 如果另一方面，任何旧的存储都没有匹配，假设负载从数据高速缓存中接收到正确的数据（假设数据缓存命中）。 传入商店根据所有年轻人的地址检查其地址。 如果与任何较小的负载相匹配，那么年轻的负载与其所有的家属一起重播。

公开(公告)号：US5958047A

公开(公告)日：1999-09-28

申请号：US881730

申请日：1997-06-25

申请人： Ramesh Panwar ,  Arjun Prabhu

发明人： Ramesh Panwar ,  Arjun Prabhu

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30094 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

摘要翻译： 一种处理器，包括产生无序结果和无序条件代码的至少一个执行单元。 通过提供具有多个时隙的结果缓冲器并提供具有与结果缓冲器相同数量的时隙的条件代码缓冲器来维持处理器的精确架构状态，条件代码缓冲器中的每个时隙与一个对应于 结果缓冲区中的一个插槽。 处理器中的每个实时指令都在结果缓冲区和条件代码缓冲区中分配一个时隙。 由执行单元产生的每个推测结果都存储在结果缓冲区中的分配时隙中。 当指令退出时，该指令的结果被传送到架构结果寄存器，并且由该指令生成的任何条件代码被传送到架构条件代码寄存器。

公开(公告)号：US5948106A

公开(公告)日：1999-09-07

申请号：US882613

申请日：1997-06-25

申请人： Ricky C. Hetherington ,  Ramesh Panwar

发明人： Ricky C. Hetherington ,  Ramesh Panwar

IPC分类号： G06F1/20 ,  G06F15/00

CPC分类号： G06F1/206

摘要： A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe. This mechanism can detect when an idle queue is suddenly overwhelmed with input such that over a short period of approximately 10-20 machine cycles, the queue activity rate has increased from idle to near stall threshold.

摘要翻译： 一种用于处理器的热过载检测和保护的系统和方法，其允许处理器在其绝大多数执行寿命期间以接近最大潜力运行。 这通过提供电路来检测何时处理器已经超过其热阈值并且然后使处理器在执行继续时自动将时钟速率降低到标称时钟的一小部分来实现。 当热条件稳定时，时钟可以逐步升高回到标称时钟速率。 在将时钟频率从标称到最小和反向的整个周期期间，程序继续执行。 还提供了一种队列活动上升时间检测器和方法，用于通过在管道中的每个阶段的边界处的局部失速机构来控制功能单元从怠速到全节气门的加速率。 这种机制可以检测空闲队列何时突然被输入压倒，使得在大约10-20个机器周期的短时间内，队列活动速率已经从空闲增加到接近失速阈值。