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1.发明授权Biasing scheme for reducing stress and improving reliability in EEPROM cells 失效用于减小应力并提高EEPROM单元可靠性的偏置方案
公开(公告)号：US5905675A
公开(公告)日：1999-05-18
申请号：US995870
申请日：1997-12-22
申请人： Raminda U. Madurawe , Richard G. Smolen , Minchang Liang , James D. Sansbury , John E. Turner , John C. Costello , Myron W. Wong
发明人： Raminda U. Madurawe , Richard G. Smolen , Minchang Liang , James D. Sansbury , John E. Turner , John C. Costello , Myron W. Wong
IPC分类号： G11C16/04 , G11C16/26 , G11C29/50 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/3427 , G11C29/50 , G11C29/50004 , H01L27/115 , H01L27/11558 , G11C16/04 , G11C16/26 , G11C2216/10
摘要： Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control gate and the write column of the cell, which reduces the tunnel oxide electric field. In a preferred embodiment, the method involves applying bias voltages to the control gate and write column of an EEPROM cell such that the potential difference between the control gate and the right column is no more than about 0.5 volts. By biasing the cell's write column to a positive voltage, the tunnel oxide field may be significantly reduced. Moreover, the invention provides a method of selecting a write column voltage based on a control gate voltage such that the tunnel oxide field is substantially balanced in all its modes. This biasing scheme minimizes SILC and improves cell reliability.
摘要翻译： 公开了一种用于偏置双行线EEPROM单元的方法。 新的偏置方案通过减小控制栅极和单元的写入列之间的电位差来改善EEPROM单元的数据保持寿命，这降低了隧道氧化物电场。 在优选实施例中，该方法包括将偏置电压施加到EEPROM单元的控制栅极和写入列，使得控制栅极与右列之间的电位差不超过约0.5伏特。 通过将单元的写入列偏置为正电压，隧道氧化物场可能会显着减少。 此外，本发明提供了一种基于控制栅极电压来选择写入列电压的方法，使得隧道氧化物场在其所有模式中基本平衡。 该偏置方案使SILC最小化，并提高了单元的可靠性。
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2.发明授权公开(公告)号：US06646919B1
公开(公告)日：2003-11-11
申请号：US09874716
申请日：2001-06-04
IPC分类号： G11C1606
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译： 公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。 简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。 本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。 在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。 或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。 电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除 电池的裕度电压进入可测量范围。
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3.发明授权公开(公告)号：US06781883B1
公开(公告)日：2004-08-24
申请号：US10620917
申请日：2003-07-15
IPC分类号： G11C1606
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译： 公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。 简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。 本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。 在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。 或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。 电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除 电池的裕度电压进入可测量范围。
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4.发明授权公开(公告)号：US06268623B1
公开(公告)日：2001-07-31
申请号：US08995873
申请日：1997-12-22
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译： 公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。 简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。 本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。 在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。 或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。 电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除 电池的裕度电压进入可测量范围。
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5.发明申请NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES 有权非易失性存储器电路，包括具有相变存储器件的电压分压器公开(公告)号：US20100177560A1
公开(公告)日：2010-07-15
申请号：US12354121
申请日：2009-01-15
IPC分类号： G11C11/00
CPC分类号： G11C14/009 , G11C13/0004
摘要： A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.
摘要翻译： 描述了包括具有第一相变存储器（PCM）装置的分压器和耦合到第一PCM装置的第二PCM装置的存储器电路。 在一个实施例中，第一PCM器件处于设定电阻状态，第二PCM器件处于复位电阻状态。 而且，在一个实施例中，分压器还包括耦合到第一PCM器件的第一开关和耦合到第一开关和第二PCM器件的第二开关。 在一个实施例中，存储器电路还包括耦合到分压器的半锁存器和耦合到半锁存器和分压器的级联晶体管。
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6.发明授权Non-volatile memory circuit including voltage divider with phase change memory devices 有权包括具有相变存储器件的分压器的非易失性存储器电路公开(公告)号：US08130538B2
公开(公告)日：2012-03-06
申请号：US12354121
申请日：2009-01-15
IPC分类号： G11C11/00
CPC分类号： G11C14/009 , G11C13/0004
摘要： A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.
摘要翻译： 描述了包括具有第一相变存储器（PCM）装置的分压器和耦合到第一PCM装置的第二PCM装置的存储器电路。 在一个实施例中，第一PCM器件处于设定电阻状态，第二PCM器件处于复位电阻状态。 而且，在一个实施例中，分压器还包括耦合到第一PCM器件的第一开关和耦合到第一开关和第二PCM器件的第二开关。 在一个实施例中，存储器电路还包括耦合到分压器的半锁存器和耦合到半锁存器和分压器的级联晶体管。
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7.发明授权
公开(公告)号：US5850365A
公开(公告)日：1998-12-15
申请号：US772567
申请日：1996-12-24
申请人： Dirk A. Reese , Myron W. Wong , John C. Costello
发明人： Dirk A. Reese , Myron W. Wong , John C. Costello
CPC分类号： G11C7/067
摘要： The present invention is a sense amplifier circuit for use with programmable logic devices that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, employs feedback circuits to further improve switching time and may be selectively operated in low power mode without significant reduction in switching speed. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.
摘要翻译： 本发明是一种与可编程逻辑器件一起使用的读出放大器电路，通过主动地限制其正在感测的位线上的电压摆幅而不是被动地感测电压来提供改进的开关时间，采用反馈电路来进一步提高开关时间， 可以选择性地在低功率模式下操作而不显着降低开关速度。 可以添加包括由参考电位供应的电位控制的可变电流限制器的电压参考控制电路，以提高抗噪声性能。 设计参考电位的电路被设计成使得其对制造变化的敏感度基本上类似于读出放大器的灵敏度，并因此相应地调整参考电位。
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公开(公告)号：US06184703B2
公开(公告)日：2001-02-06
申请号：US09092240
申请日：1998-06-05
IPC分类号： H03K1716
CPC分类号： H03K19/00361
摘要： An output buffer comprising control circuit for reducing the amount of ground and/or power bounce noise. The output buffer further includes one or more driver devices. The output current of the driver device(s) is limited by providing an intermediate drive voltage to the control electrode of the driver device. A pass device (or a transmission gate) provides the intermediate drive voltage and also operates as a variable resistive device that limits the slew rate of the drive voltage. The operation of the pass device can be dependent on a signal level at the output of the output buffer. When the output has transitioned to a new logic state, the new logic level is fed back to change the operating state of the pass device, thus ensuring that the output voltage meets the output VOL and VOH specifications.
摘要翻译： 一种输出缓冲器，包括用于减少接地和/或功率反弹噪声量的控制电路。 输出缓冲器还包括一个或多个驱动器装置。 通过向驱动器装置的控制电极提供中间驱动电压来限制驱动器装置的输出电流。 通过装置（或传输门）提供中间驱动电压，并且还用作限制驱动电压的转换速率的可变电阻装置。 通过设备的操作可以取决于输出缓冲器输出端的信号电平。 当输出转换到新的逻辑状态时，反馈新的逻辑电平以改变通过器件的工作状态，从而确保输出电压满足输出VOL和VOH规范。
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公开(公告)号：US5525917A
公开(公告)日：1996-06-11
申请号：US358210
申请日：1994-12-16
申请人： Myron W. Wong , Dirk A. Reese , John C. Costello
发明人： Myron W. Wong , Dirk A. Reese , John C. Costello
CPC分类号： G11C7/067
摘要： The present invention is a sense amplifier circuit for use with programmable logic devices, that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, and that employs feedback circuits to further improve switching time. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.
摘要翻译： 本发明是一种与可编程逻辑器件一起使用的读出放大器电路，其通过主动地限制其感测的位线上的电压摆幅来提供改进的开关时间，而不是被动地感测电压，并且采用反馈电路进一步改进 切换时间。 可以添加包括由参考电位供应的电位控制的可变电流限制器的电压参考控制电路，以提高抗噪声性能。 设计参考电位的电路被设计成使得其对制造变化的敏感度基本上类似于读出放大器的灵敏度，并因此相应地调整参考电位。
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公开(公告)号：US06242941B1
公开(公告)日：2001-06-05
申请号：US09320858
申请日：1999-05-26
申请人： W. Bradley Vest , Mark W. Fiester , Myron W. Wong , John C. Costello , Robert R. N. Bielby , Krishna Rangasayee
发明人： W. Bradley Vest , Mark W. Fiester , Myron W. Wong , John C. Costello , Robert R. N. Bielby , Krishna Rangasayee
IPC分类号： H03K1716
CPC分类号： H03K19/00346
摘要： An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user mode. In an implementation, the integrated circuit (125) is configurable in the programming mode with user configuration data. In the user mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output (210) of the integrated circuit will switch to its user mode value. In order to minimize switching noise, the outputs are released to their user mode values not all at the same time.
摘要翻译： 集成电路包含以这种方式操作以在将输出电路从编程模式切换到用户模式时降低输出噪声的电路。 在实现中，集成电路（125）可以在具有用户配置数据的编程模式下配置。 在用户模式下，集成电路将以编程模式下用户定义的功能运行。 当从编程模式切换到用户模式时，集成电路的每个输出（210）将切换到其用户模式值。 为了最小化开关噪声，输出不会全部被释放到用户模式值。
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