公开(公告)号：US06927445B2

公开(公告)日：2005-08-09

申请号：US09921423

申请日：2001-08-02

申请人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

发明人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

IPC分类号： H01L21/02 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L28/87 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprises a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch-resistant material, and etching the alternating layers, thereby forming a capacitor structure having corrugated sides.

摘要翻译： 一种在半导体部件上形成波纹状电容器的方法。 形成波纹状电容器的方法包括在半导体组件上具有不同蚀刻速率的一系列沉积交替层的掺杂硅玻璃，用耐蚀刻材料覆盖交替层，并蚀刻交替层，从而形成具有 波纹状。

公开(公告)号：US06346455B1

公开(公告)日：2002-02-12

申请号：US09651946

申请日：2000-08-31

申请人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

发明人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

IPC分类号： H01L2120

CPC分类号： H01L28/87 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprising a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch resistant material, and etching the alternating layers thereby forming a capacitor structure having corrugated sides.

摘要翻译： 一种在半导体部件上形成波纹状电容器的方法。 形成波纹状电容器的方法包括在半导体组件上具有不同蚀刻速率的一系列沉积交替层的掺杂硅玻璃，用抗蚀刻材料覆盖交替层，并且蚀刻交替层，从而形成具有波纹状的电容器结构 。

公开(公告)号：US06660611B2

公开(公告)日：2003-12-09

申请号：US10010842

申请日：2001-12-07

申请人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

发明人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

IPC分类号： H01L2120

CPC分类号： H01L28/87 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprises a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch-resistant material, and etching the alternating layers, thereby forming a capacitor structure having corrugated sides.

摘要翻译： 一种在半导体部件上形成波纹状电容器的方法。 形成波纹状电容器的方法包括在半导体组件上具有不同蚀刻速率的一系列沉积交替层的掺杂硅玻璃，用耐蚀刻材料覆盖交替层，并蚀刻交替层，从而形成具有 波纹状。

公开(公告)号：US20150279851A1

公开(公告)日：2015-10-01

申请号：US14227217

申请日：2014-03-27

申请人： Darwin Fan ,  Sateesh Koka ,  Gordon Haller ,  John Hopkins ,  Shyam Surthi ,  Anish Khandekar

发明人： Darwin Fan ,  Sateesh Koka ,  Gordon Haller ,  John Hopkins ,  Shyam Surthi ,  Anish Khandekar

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11556

摘要： 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

摘要翻译： 提供3D NAND存储器结构及相关方法。 在一些实施例中，这样的结构可以包括设置在第一绝缘层和第二绝缘层之间的控制栅极材料和浮置栅极材料，设置在浮置栅极材料和控制栅极材料之间的多层电介质（IPD）层，使得IPD层 将控制栅极材料与浮动栅极材料电隔离，以及沉积在与控制栅极材料相对的浮动栅极材料上的隧道电介质材料。

公开(公告)号：US20130168756A1

公开(公告)日：2013-07-04

申请号：US13343087

申请日：2012-01-04

申请人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

发明人： John Hopkins ,  James Mathew ,  Jie Sun ,  Gordon Haller

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

摘要： Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

摘要翻译： 公开了设备，存储器阵列和方法。 在一个实施例中，一个这样的器件具有源极/漏极区域，其具有第一和第二有源区域，以及在第一和第二有源区域之间的隔离区域和电介质插塞。 电介质插塞可以延伸到第一和第二有源区域的上表面之下，并且可以由对于特定各向同性去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US08222105B2

公开(公告)日：2012-07-17

申请号：US12703502

申请日：2010-02-10

申请人： Gordon Haller ,  Sanh D. Tang ,  Steve Cummings

发明人： Gordon Haller ,  Sanh D. Tang ,  Steve Cummings

IPC分类号： H01L29/94

CPC分类号： H01L21/823487 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

摘要翻译： 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。 在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

公开(公告)号：US08076721B2

公开(公告)日：2011-12-13

申请号：US12795495

申请日：2010-06-07

申请人： Sahn D. Tang ,  Gordon Haller

发明人： Sahn D. Tang ,  Gordon Haller

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

摘要： There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

摘要翻译： 提供了用于制造翅片结构的翅片结构和方法。 更具体地，翅片结构形成在基板中。 翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。 翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

公开(公告)号：US07589995B2

公开(公告)日：2009-09-15

申请号：US11516814

申请日：2006-09-07

申请人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

发明人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

IPC分类号： G11C11/34

CPC分类号： H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

摘要翻译： 单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。

公开(公告)号：US20070166920A1

公开(公告)日：2007-07-19

申请号：US11716433

申请日：2007-03-08

申请人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

发明人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。

公开(公告)号：US20070048941A1

公开(公告)日：2007-03-01

申请号：US11219077

申请日：2005-09-01

申请人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

发明人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.