摘要:
3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
摘要:
3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
摘要:
Methods are disclosed for forming connections to a memory array and a periphery of the array. The methods include forming stacks of conductive materials on the array and the periphery and forming a step between the periphery stack and the array stack. The step is removed during subsequent processing, and connections are formed from the conductive materials remaining on the array and the periphery. In some embodiments, the step is removed before any photolithographic processes.
摘要:
Several embodiments of systems for depositing materials and associated methods of operation are disclosed herein. In one embodiment, the system includes a reaction chamber having an inlet and an outlet, a gas source coupled to the inlet of the reaction chamber, and a neutralizer source coupled to the outlet of the reaction chamber. The gas source contains a first precursor gas, a second precursor gas, and a purge gas. The neutralizer source contains a neutralizing agent configured to reduce a rate of reaction between the first precursor gas and the second precursor gas.
摘要:
A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Conductive material received over the trench sidewall portion is covered with a silicon nitride-comprising layer which less than fills remaining trench volume. The insulative material within the array area and the silicon nitride-comprising layer are etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
摘要:
Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process.
摘要:
A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Conductive material received over the trench sidewall portion is covered with a silicon nitride-comprising layer which less than fills remaining trench volume. The insulative material within the array area and the silicon nitride-comprising layer are etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
摘要:
Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
摘要:
Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
摘要:
Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods.