-
公开(公告)号：US5789973A
公开(公告)日：1998-08-04
申请号：US707673
申请日：1996-09-04
CPC分类号： H03H11/0422
摘要： A resistorless amplifier circuit uses integrated operational transconductance amplifiers to realize a plurality of circuit transfer functions. The preferred embodiment produces an output signal voltage V.sub.out (500) that is either g.sub.m1 /g.sub.m3 or g.sub.m1 /(g.sub.m3 -g.sub.m1) times the input signal voltage V.sub.in (400). Additionally, an alternative embodiment implements a resistorless summing and subtracting operational transconductance amplifier circuit that realizes an output signal voltage as follows: ##EQU1## The resistorless amplifier circuit includes a first operational transconductance amplifier (100) with a transconductance g.sub.m1, a second operational transconductance amplifier (200) with a transconductance g.sub.m2, and a third operational transconductance amplifier (300) with a transconductance g.sub.m3.
摘要翻译： 无阻抗放大器电路使用集成的运算跨导放大器来实现多个电路传输功能。 优选实施例产生输入信号电压Vin（400）的输出信号电压Vout（500），其为gm1 / gm3或gm1 /（gm3-gm1）倍。 另外，替代实施例实现如下实现无输出信号电压的无阻抗求和运算跨导放大器电路：无图像放大器电路包括具有跨导gm1的第一运算跨导放大器（100），第二运算跨导放大器 （200）和具有跨导gm3的第三操作跨导放大器（300）。
-
公开(公告)号：US5576664A
公开(公告)日：1996-11-19
申请号：US556882
申请日：1995-11-02
申请人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
发明人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
摘要： A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).
摘要翻译： 通信接收器（100）采用离散时间数字锁相环（142）来保持锁定到参考信号（136）的生成信号（144）。 离散时间数字锁相环（142）包括相位检测器（202），累加器（219），加法器（227）和受控振荡器（232）。 累加器（219）连接到相位检测器（202）和参考信号（136），用于计算等于由相位检测器（202）生成的当前采样的第一和的累加器输出值，并且所有多个 在当前样本之前产生的离散相位误差样本。 加法器（227）连接到相位检测器（202）和累加器（219），用于形成当前采样和累加器输出值的第二和。 受控振荡器（232）接收用于控制受控振荡器（232）的第二和。
-
3.发明授权Method and apparatus for generating multiple signals at multiple frequencies 失效用于在多个频率上产生多个信号的方法和装置
公开(公告)号：US5630222A
公开(公告)日：1997-05-13
申请号：US566518
申请日：1995-12-04
摘要： A frequency synthesizer (100) is used for generating a plurality of signals operating at a plurality of frequencies that are integer multiples of a reference frequency. The frequency synthesizer (100) includes a plurality of phase lock loops coupled to a single phase error detector. The phase error detector (103) is connected to a reference signal (104), a first generated signal (116) and a sampler signal (136) derived from a second generated signal (132). The phase error detector (103) includes a shared counter (118), and first and second registers (106, 122) connected to the output of the shared counter (118). First and second phase lock loops (101, 105) are used for phase locking to the reference signal (104). The first and second phase lock loops (101, 105) derive phase error signals from the first and second registers (106, 122), thereby adjusting the first and second generated signals (116, 132).
摘要翻译： 频率合成器（100）用于产生以参考频率的整数倍的多个频率工作的多个信号。 频率合成器（100）包括耦合到单相误差检测器的多个锁相环。 相位误差检测器（103）连接到从第二生成信号（132）导出的参考信号（104），第一生成信号（116）和取样器信号（136）。 相位误差检测器（103）包括共享计数器（118）以及连接到共享计数器（118）的输出的第一和第二寄存器（106,122）。 第一和第二锁相环（101,105）用于相位锁定到参考信号（104）。 第一和第二锁相环（101,105）从第一和第二寄存器（106,122）导出相位误差信号，从而调整第一和第二产生信号（116,132）。
-
公开(公告)号：US5412336A
公开(公告)日：1995-05-02
申请号：US150660
申请日：1993-11-10
CPC分类号： H03F1/223
摘要： A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.
摘要翻译： 一种级联放大器电路，包括响应于输入信号产生第一输出电流（403）的输入镜像晶体管（401）。 二极管连接的晶体管（404）产生与第一输出电流成比例的控制偏置。 共源共栅连接的晶体管输出级（405）包括耦合到输入信号的公共源晶体管（406）和用于在共源共栅连接的晶体管输出级中建立输出电流（407）的输入镜像晶体管（401）。 公共栅极晶体管（408）耦合到二极管连接的晶体管（404）和公共源极晶体管（406），用于将公共源极晶体管（406）与存在于输出端子（409）处的输出电压的任何变化隔离 公共栅极晶体管（408）在操作时响应于控制偏压来控制当前的输出（407）。
-
5.发明授权Method and apparatus for determining an instantaneous phase difference between two signals 失效用于确定两个信号之间的瞬时相位差的方法和装置
公开(公告)号：US5552750A
公开(公告)日：1996-09-03
申请号：US523665
申请日：1995-09-05
CPC分类号： H03L7/183 , H03D13/001 , H03L7/091
摘要： A method and apparatus determine an instantaneous phase difference (207) between a reference signal (103) and a controlled signal (120). The reference signal (103) is derived by frequency dividing a first signal by a counter (106) including an output (107) having K sequential states, wherein K is an integer value equal to the frequency of the first signal (103) divided by the frequency of the desired reference signal, and wherein the output (107) changes by no more than one bit between any adjacent states of the K sequential states. The output (107) of the counter (106) is recorded (206) at a time concurrent with a first predetermined event occurring in the controlled signal (120), thereby generating a recorded count value that is free from metastability induced errors. The recorded count value is decoded (208) to produce a sequential state number S.sub.E corresponding to the first predetermined event. The instantaneous phase difference (207) is then calculated (210) from S.sub.E, K, and other predetermined constants.
摘要翻译： 方法和装置确定参考信号（103）和受控信号（120）之间的瞬时相位差（207）。 参考信号（103）是通过用包括具有K个顺序状态的输出（107）的计数器（106）对第一信号进行分频而导出的，其中K是等于第一信号（103）的频率的整数值除以 所述参考信号的频率，并且其中所述输出（107）在所述K个顺序状态的任何相邻状态之间改变不超过一个比特。 与受控信号（120）中发生的第一预定事件同时记录（206）计数器（106）的输出（107），从而生成没有亚稳引起的误差的记录计数值。 记录的计数值被解码（208）以产生对应于第一预定事件的顺序状态号码SE。 然后从SE，K和其他预定常数计算（210）瞬时相位差（207）。
-
公开(公告)号：US5337007A
公开(公告)日：1994-08-09
申请号：US147235
申请日：1993-11-04
CPC分类号： H03F3/3001 , H03F3/45076
摘要： A class AB transconductance amplifier (200) has first and second differential input amplifier stages (100-112) adapted for receiving first and second differential input signals (Vin+, Vin-). First and second input cascode stages are coupled to the first and second differential input amplifier stages for providing first and second differential folded cascode signals. An output stage (113-118) is coupled to the first and second differential folded cascode signals providing an output signal indicative of a difference between the first and second differential input signals (Vin+, Vin-). A bias stage (101, 102) is coupled to said first and second differential input amplifier stages (103-104, 105-106) and the first and second input cascode stages bias the first and second differential input amplifier stages (100-112) to operate as a class AB folded cascode amplifier circuit (200). The bias stage generates class AB biasing signals.
摘要翻译： AB类跨导放大器（200）具有适于接收第一和第二差分输入信号（Vin +，Vin-）的第一和第二差分输入放大器级（100-112）。 第一和第二输入共源共栅级耦合到第一和第二差分输入放大器级，以提供第一和第二差分折叠共源共栅信号。 输出级（113-118）耦合到第一和第二差分折叠共源共栅信号，提供表示第一和第二差分输入信号（Vin +，Vin-）之间的差的输出信号。 偏置级（101,102）耦合到所述第一和第二差分输入放大器级（103-104,10-10-106），并且第一和第二输入共源共栅级偏置第一和第二差分输入放大器级（100-112） 作为AB折叠共源共栅放大器电路（200）操作。 偏置级产生AB类偏置信号。
-
公开(公告)号：US5373249A
公开(公告)日：1994-12-13
申请号：US150930
申请日：1993-11-10
CPC分类号： H03F3/3001
摘要： A complementary cascode push-pull amplifier circuit includes a bias generator, a complementary bias generator, a cascode input stage (416, 417), a cascode output stage (410, 411), a complementary cascode input stage (456,457), and a complementary cascode output stage (450,451). The bias generator is responsive to a first input signal (420) and generates a bias control voltage. The complementary bias generator is responsive to a second input (421) and generates a complementary bias control voltage. The cascode output stage (410, 411) and the complementary cascode output stage (450,451) each have an output coupled to a common output terminal (510) for generating a portion of an output current signal in response to the respective input signals (420, 421) and in response to the bias control voltage and the complementary bias control voltage being generated.
摘要翻译： 互补共源共栅放大器电路包括偏置发生器，互补偏置发生器，共源共栅输入级（416,417），共源共栅输出级（410,411），互补共源共栅输入级（456,457）和互补 共源共栅输出级（450,451）。 偏置发生器响应于第一输入信号（420）并产生偏置控制电压。 互补偏置发生器响应于第二输入（421）并产生互补偏置控制电压。 级联输出级（410,411）和互补共源共栅输出级（450,451）各自具有耦合到公共输出端（510）的输出，用于响应于相应的输入信号（420,411）产生输出电流信号的一部分， 并且响应于所产生的偏置控制电压和互补偏置控制电压。
-
公开(公告)号：US5363061A
公开(公告)日：1994-11-08
申请号：US152991
申请日：1993-11-10
CPC分类号： H03F3/347
摘要： A multi-output integrated circuit amplifier (500) consists of a first primary current mirror (510), and a plurality of secondary current mirrors (520). The first primary current mirror (510) implemented in a single substrate and having a first primary input (511). The first primary current mirror (510) generates a plurality of first inverted primary current outputs in response to a first current signal coupled to the first primary input (511). The plurality of secondary current mirrors are implemented in the same single substrate and each has a secondary input coupled to a unique one of the plurality of primary current outputs of the first primary current mirror (510), each of said plurality of secondary current mirrors (520) having a gain, and each of said plurality of secondary current mirrors (520) generating an inverted secondary current output signal, the magnitude of which is determined substantially by the unique one of the plurality of primary current outputs coupled thereto and the gain thereof.
摘要翻译： 多输出集成电路放大器（500）由第一初级电流镜（510）和多个次级电流镜（520）组成。 第一初级电流镜（510）实现在单个衬底中并具有第一主要输入（511）。 响应于耦合到第一主输入端的第一电流信号，第一初级电流镜510产生多个第一反相一次电流输出。 多个次级电流镜被实现在相同的单个衬底中，并且每个都具有耦合到第一初级电流镜（510）的多个初级电流输出中的唯一一个的次级输入，所述多个次级电流镜 520），并且所述多个次级电流镜（520）中的每一个产生反相的次级电流输出信号，其大小基本上由耦合到其的多个初级电流输出中唯一的一个确定，并且其增益 。
-
公开(公告)号：US5422911A
公开(公告)日：1995-06-06
申请号：US121857
申请日：1993-09-17
IPC分类号： H03L7/089 , H03L7/093 , H03L7/107 , H03L7/183 , H04L27/152
CPC分类号： H03L7/183 , H03L7/0891 , H03L7/093 , H03L7/107 , H03L2207/04 , H03L2207/06
摘要： A selective call receiver (100) includes a phase lock loop frequency synthesizer having a programmable output frequency signal (414) responsive to a control current signal (417). The phase lock loop frequency synthesizer includes a programmable gain current multiplier (412), a gain of which is determined by a control word selected such that a loop gain of the synthesizer remains relatively constant over a predetermined operating domain of a programmable output frequency signal (417). The current multiplier generates (412) the control current signal (417) by subtracting a reference current (415) from a limited current (416), thus bounding a range of the control current signal (417) within a maximum value of substantially the reference current (415) and a minimum value of the difference between the reference current (415) and the limited current (416).
摘要翻译： 选择呼叫接收机（100）包括具有响应于控制电流信号（417）的可编程输出频率信号（414）的锁相环频率合成器。 锁相环频率合成器包括可编程增益电流乘法器（412），其增益由所选择的控制字确定，使得合成器的环路增益在可编程输出频率信号的预定操作域上保持相对恒定（ 417）。 电流乘法器通过从受限电流（416）减去参考电流（415）来产生（412）控制电流信号（417），从而将控制电流信号（417）的范围限定在基本上为参考的最大值内 电流（415）和参考电流（415）与受限电流（416）之间的差的最小值。
-
公开(公告)号：US5361040A
公开(公告)日：1994-11-01
申请号：US138117
申请日：1993-10-20
CPC分类号： H03F3/3027 , H03F3/45192 , H03F3/45713
摘要： An operational transconductance amplifier (38) is coupled to first and second supply voltages (41, 42) for converting differential input signals into a proportional output current. The operational transconductance amplifier (38) has a predetermined common mode input range, and a differential amplifier input stage (28, 29) having a non-inverting input (Vin+), and an inverting input (Vin-). The non-inverting and inverting inputs (Vin+, Vin-) receives differential input signals. Parallel connected transistors (36, 37) are coupled to the differential amplifier input stage (28, 29) for receiving the differential input signals. A current mirror (20-23) has first and second current paths, wherein the first current path sinks a common mode current from the differential amplifier stage, and wherein the second current path diverts the common mode current from the differential amplifier input stage (28, 29) in the event that the differential input signals fall below a predetermined magnitude.
摘要翻译： 运算跨导放大器（38）耦合到第一和第二电源电压（41,42），用于将差分输入信号转换成比例输出电流。 运算跨导放大器（38）具有预定的共模输入范围，以及具有非反相输入（Vin +）和反相输入（Vin-）的差分放大器输入级（28,29）。 同相和反相输入（Vin +，Vin-）接收差分输入信号。 并联连接的晶体管（36,37）被耦合到差分放大器输入级（28,29），用于接收差分输入信号。 电流镜（20-23）具有第一和第二电流路径，其中第一电流路径从差分放大器级吸收共模电流，并且其中第二电流路径将来自差分放大器输入级（28）的共模电流 ，29）在差分输入信号低于预定幅度的情况下。
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.02 秒)
