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公开(公告)号：US07791168B2
公开(公告)日：2010-09-07
申请号：US11930698
申请日：2007-10-31
IPC分类号： H01L29/00 , H01L23/52 , H01L23/04 , H01L23/053
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device includes at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device including at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein includes the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其中包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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公开(公告)号：US07691669B2
公开(公告)日：2010-04-06
申请号：US12056852
申请日：2008-03-27
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L21/8242
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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公开(公告)号：US07488624B2
公开(公告)日：2009-02-10
申请号：US12056808
申请日：2008-03-27
IPC分类号： H01L21/82
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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公开(公告)号：US07435627B2
公开(公告)日：2008-10-14
申请号：US11201572
申请日：2005-08-11
IPC分类号： H01L21/82
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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公开(公告)号：US20080182359A1
公开(公告)日：2008-07-31
申请号：US12056852
申请日：2008-03-27
IPC分类号： H01L21/00
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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公开(公告)号：US20080176411A1
公开(公告)日：2008-07-24
申请号：US12056773
申请日：2008-03-27
IPC分类号： H01L21/31
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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公开(公告)号：US20080182361A1
公开(公告)日：2008-07-31
申请号：US12056808
申请日：2008-03-27
IPC分类号： H01L21/02
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
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公开(公告)号：US07741231B2
公开(公告)日：2010-06-22
申请号：US12056773
申请日：2008-03-27
IPC分类号： H01L21/31
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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9.发明申请STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER 审中-公开通过硅载体连接创造可靠深度的结构和方法公开(公告)号：US20080179755A1
公开(公告)日：2008-07-31
申请号：US11669924
申请日：2007-01-31
申请人： Paul S. Andry , L. Paivikki Buchwalter , Anurag Jain , John U. Knickerbocker , Edmund J. Sprogis , Michelle L. Steen , Cornelia K. Tsang
发明人： Paul S. Andry , L. Paivikki Buchwalter , Anurag Jain , John U. Knickerbocker , Edmund J. Sprogis , Michelle L. Steen , Cornelia K. Tsang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译： 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。
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10.发明授权公开(公告)号：US08592932B2
公开(公告)日：2013-11-26
申请号：US13430195
申请日：2012-03-26
IPC分类号： H01L31/0203
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
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