PROGRAMMABLE DIGITAL TDI EO/IR SCANNING FOCAL PLANE ARRAY WITH MULTIPLE SELECTABLE TDI SUB-BANKS

    公开(公告)号:US20210105425A1

    公开(公告)日:2021-04-08

    申请号:US17091689

    申请日:2020-11-06

    Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

    METHOD AND APPARATUS FOR INCREASING PIXEL SENSITIVITY AND DYNAMIC RANGE
    2.
    发明申请
    METHOD AND APPARATUS FOR INCREASING PIXEL SENSITIVITY AND DYNAMIC RANGE 有权
    增加像素灵敏度和动态范围的方法和装置

    公开(公告)号:US20160134820A1

    公开(公告)日:2016-05-12

    申请号:US14536733

    申请日:2014-11-10

    CPC classification number: H04N5/3559 H04N5/3745 H04N5/37452

    Abstract: According to one aspect, embodiments herein provide a unit cell comprising a photodiode, a MOSCap having an input node coupled to the photodiode, a reset switch selectively coupled between the MOSCap and a reset voltage, and a transistor coupled to the input node of the MOSCap, wherein, in a first mode of operation of the unit cell, the reset switch is configured in an open state and charge generated by light incident on the photodiode accumulates at the input node of the MOSCap in response to voltage at the input node being less than a threshold voltage, and wherein, in a second mode of operation of the unit cell, the reset switch is configured in the open state and the charge generated by the light incident on the photodiode accumulates on the MOSCap in response to the voltage at the input node being greater than the threshold voltage.

    Abstract translation: 根据一个方面,本文的实施例提供了一种单元单元,其包括光电二极管,具有耦合到光电二极管的输入节点的MOSCap,选择性地耦合在MOSCap和复位电压之间的复位开关以及耦合到MOSCap的输入节点的晶体管 ,其中在所述单电池的第一操作模式中,所述复位开关被配置为处于断开状态,并且响应于所述输入节点处的电压而在所述MOSCap的输入节点处累积的入射到所述光电二极管上的光产生的电荷累积 并且其中,在所述单位电池的第二工作模式中,所述复位开关被配置为处于打开状态,并且由入射到所述光电二极管上的光产生的电荷响应于所述MOSCap处的电压积累在所述MOSCap上 输入节点大于阈值电压。

    Method and apparatus for increasing pixel sensitivity and dynamic range

    公开(公告)号:US09774802B2

    公开(公告)日:2017-09-26

    申请号:US14536733

    申请日:2014-11-10

    CPC classification number: H04N5/3559 H04N5/3745 H04N5/37452

    Abstract: According to one aspect, embodiments herein provide a unit cell comprising a photodiode, a MOSCap having an input node coupled to the photodiode, a reset switch selectively coupled between the MOSCap and a reset voltage, and a transistor coupled to the input node of the MOSCap, wherein, in a first mode of operation of the unit cell, the reset switch is configured in an open state and charge generated by light incident on the photodiode accumulates at the input node of the MOSCap in response to voltage at the input node being less than a threshold voltage, and wherein, in a second mode of operation of the unit cell, the reset switch is configured in the open state and the charge generated by the light incident on the photodiode accumulates on the MOSCap in response to the voltage at the input node being greater than the threshold voltage.

    METHOD AND SYSTEM FOR MANAGING DEFECTS IN FOCAL PLANE ARRAYS USING REDUNDANT COMPONENTS
    4.
    发明申请
    METHOD AND SYSTEM FOR MANAGING DEFECTS IN FOCAL PLANE ARRAYS USING REDUNDANT COMPONENTS 审中-公开
    管理使用冗余组件的正面平面阵列缺陷的方法和系统

    公开(公告)号:US20150288907A1

    公开(公告)日:2015-10-08

    申请号:US14244032

    申请日:2014-04-03

    Abstract: A focal plane array having: an imaging array section, comprising: an array of electromagnetic radiation detectors; and an address section providing outputs from selectively enabled detectors. The imaging array section comprises a plurality of circuit blocks, each one of the circuit blocks having a primary circuit and a redundant circuit. Test circuitry is for provided for supplying test signals to test each one of the primary circuits and determining whether a response from the test signals is proper or improper and for storing in the test circuitry in response to such determining select signals associated with each one of the tested circuit blocks. An array controller is provided for, during a subsequent normal operating mode, providing timing pulses to the address section wherein the address section selectively enables the detectors using either the primary or redundant circuits in the plurality of circuit blocks selectively in accordance with the stored select signals.

    Abstract translation: 1.一种焦平面阵列,具有:成像阵列部,包括:电磁辐射检测器阵列; 以及提供来自选择性启用的检测器的输出的地址部分。 成像阵列部分包括多个电路块,每个电路块具有主电路和冗余电路。 测试电路用于提供测试信号以测试主电路中的每一个,并且确定来自测试信号的响应是否适当或不正确,并且响应于这样的确定选择信号而存储在测试电路中 测试电路块。 提供阵列控制器,用于在随后的正常操作模式期间向地址部分提供定时脉冲,其中地址部分根据存储的选择信号有选择地使能多个电路块中的主电路或冗余电路的检测器 。

    ARTIFACT MITIGATION IN CAPACITOR TRANSIMPEDANCE AMPLIFIER (CTIA)-BASED IMAGERS OR OTHER IMAGING DEVICES

    公开(公告)号:US20240267655A1

    公开(公告)日:2024-08-08

    申请号:US18165663

    申请日:2023-02-07

    Inventor: Bryan W. Kean

    CPC classification number: H04N25/778 H03F3/087 H04N25/709

    Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a first reference voltage and generate a pre-integration voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, (iii) a reset switch coupled in parallel across the feedback capacitor, and (iv) a coupling capacitor coupled to an output of the amplifier and configured to receive the pre-integration voltage and generate an integration voltage. The apparatus further includes a comparator configured to compare the pre-integration voltage and a second reference voltage, where generation of the integration voltage is modifiable based on the comparison.

    HIGH FLUX DETECTION AND IMAGING USING CAPACITOR TRANSIMPEDANCE AMPLIFIER (CTIA)-BASED UNIT CELLS IN IMAGING DEVICES

    公开(公告)号:US20240267006A1

    公开(公告)日:2024-08-08

    申请号:US18165713

    申请日:2023-02-07

    Inventor: Bryan W. Kean

    CPC classification number: H03F3/087 H03F1/083 H03F3/005 H03F2203/45551

    Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell configured to generate an integration voltage based on the electrical current. The CTIA unit cell includes (i) an amplifier configured to receive the electrical current and a first reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes a comparator configured to compare an input voltage of the amplifier and a second reference voltage, where generation of the integration voltage is modifiable based on the comparison.

    High-energy suppression for capacitor transimpedance amplifier (CTIA)-based imagers or other imaging devices

    公开(公告)号:US11843355B2

    公开(公告)日:2023-12-12

    申请号:US17649994

    申请日:2022-02-04

    CPC classification number: H03F3/087 H03F1/08 H03F3/70

    Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

    Read out integrated circuit
    9.
    发明授权
    Read out integrated circuit 有权
    读出集成电路

    公开(公告)号:US08686766B2

    公开(公告)日:2014-04-01

    申请号:US13764483

    申请日:2013-02-11

    Abstract: According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.

    Abstract translation: 根据一个实施例,电路包括电容反阻抗放大器(CTIA),其被配置为在输入处接收电流脉冲并将电流脉冲转换成电压阶跃。 电压步骤被引导到第一信号路径和第二信号路径。 当电压步长超过第一阈值时,第一信号路径将使能脉冲引导到第二信号路径。 第二信号路径当电压步长超过第二阈值时产生输出脉冲,使能脉冲使能。 第二信号路径包括第一,第二和第三放大器,以增加第二信号路径对电压步进的检测。

    READ OUT INTEGRATED CIRCUIT
    10.
    发明申请
    READ OUT INTEGRATED CIRCUIT 有权
    读出集成电路

    公开(公告)号:US20140062602A1

    公开(公告)日:2014-03-06

    申请号:US13764483

    申请日:2013-02-11

    Abstract: According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.

    Abstract translation: 根据一个实施例,电路包括电容反阻抗放大器(CTIA),其被配置为在输入处接收电流脉冲并将电流脉冲转换成电压阶跃。 电压步骤被引导到第一信号路径和第二信号路径。 当电压步长超过第一阈值时,第一信号路径将使能脉冲引导到第二信号路径。 第二信号路径当电压步长超过第二阈值时产生输出脉冲,使能脉冲使能。 第二信号路径包括第一,第二和第三放大器,以增加第二信号路径对电压步进的检测。

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