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公开(公告)号:US20170005080A1
公开(公告)日:2017-01-05
申请号:US15268742
申请日:2016-09-19
Applicant: Renesas Electronics Corporation
Inventor: Bunji YASUMURA , Yoshinori DEGUCHI , Fumikazu TAKEI , Akio HASEBE , Naohiro MAKIHIRA , Mitsuyuki KUBO
IPC: H01L25/00 , H01L23/00 , H01L23/544 , H01L25/18 , H01L25/065
CPC classification number: H01L25/50 , H01L21/6835 , H01L22/12 , H01L22/14 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2223/54426 , H01L2223/5448 , H01L2223/54493 , H01L2224/03002 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/06131 , H01L2224/11009 , H01L2224/13025 , H01L2224/13082 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06593 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/16251 , H01L2924/181 , H01L2224/11 , H01L2924/00
Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
Abstract translation: 当存储器芯片安装在逻辑芯片上时,将形成在逻辑芯片的背面的识别标记的识别范围成像,识别范围的形状,逻辑芯片的多个凸点与 基于识别的结果执行上述存储芯片的多个投影电极,并且将上述存储芯片安装在逻辑芯片上。 此时,识别范围的形状与凸块的阵列形状的任何部分不同,结果,可以可靠地识别识别范围形状的识别标记,并且逻辑的凸块的对准 高精度地执行上述存储芯片的芯片和投影电极。
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公开(公告)号:US20180040598A1
公开(公告)日:2018-02-08
申请号:US15730977
申请日:2017-10-12
Applicant: Renesas Electronics Corporation
Inventor: Bunji YASUMURA , Yoshinori DEGUCHI , Fumikazu TAKEI , Akio HASEBE , Naohiro MAKIHIRA , Mitsuyuki KUBO
IPC: H01L25/00 , H01L21/66 , H01L23/544 , H01L21/683 , H01L25/18 , H01L23/00 , H01L25/065
CPC classification number: H01L25/50 , H01L21/6835 , H01L22/12 , H01L22/14 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2223/54426 , H01L2223/5448 , H01L2223/54493 , H01L2224/03002 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/06131 , H01L2224/11009 , H01L2224/13025 , H01L2224/13082 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06593 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/16251 , H01L2924/181 , H01L2224/11 , H01L2924/00
Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
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