公开(公告)号：US20170005080A1

公开(公告)日：2017-01-05

申请号：US15268742

申请日：2016-09-19

Applicant: Renesas Electronics Corporation

Inventor： Bunji YASUMURA ,  Yoshinori DEGUCHI ,  Fumikazu TAKEI ,  Akio HASEBE ,  Naohiro MAKIHIRA ,  Mitsuyuki KUBO

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/544 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L22/12 ,  H01L22/14 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2223/54493 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/11009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00

Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract translation: 当存储器芯片安装在逻辑芯片上时，将形成在逻辑芯片的背面的识别标记的识别范围成像，识别范围的形状，逻辑芯片的多个凸点与 基于识别的结果执行上述存储芯片的多个投影电极，并且将上述存储芯片安装在逻辑芯片上。 此时，识别范围的形状与凸块的阵列形状的任何部分不同，结果，可以可靠地识别识别范围形状的识别标记，并且逻辑的凸块的对准 高精度地执行上述存储芯片的芯片和投影电极。

公开(公告)号：US20180040521A1

公开(公告)日：2018-02-08

申请号：US15785531

申请日：2017-10-17

Applicant: Renesas Electronics Corporation

Inventor： Bunji YASUMURA ,  Fumio TSUCHIYA ,  Hisanori ITO ,  Takuji IDE ,  Naoki KAWANABE ,  Masanao SATO

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

公开(公告)号：US20180040598A1

公开(公告)日：2018-02-08

申请号：US15730977

申请日：2017-10-12

Applicant: Renesas Electronics Corporation

Inventor： Bunji YASUMURA ,  Yoshinori DEGUCHI ,  Fumikazu TAKEI ,  Akio HASEBE ,  Naohiro MAKIHIRA ,  Mitsuyuki KUBO

IPC: H01L25/00 ,  H01L21/66 ,  H01L23/544 ,  H01L21/683 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L22/12 ,  H01L22/14 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2223/54493 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/11009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00

Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

公开(公告)号：US20170018470A1

公开(公告)日：2017-01-19

申请号：US15280618

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Bunji YASUMURA ,  Fumio TSUCHIYA ,  Hisanori ITO ,  Takuji IDE ,  Naoki KAWANABE ,  Masanao SATO

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

Abstract translation: 提供了能够防止半导体装置的最上层的保护膜的破裂的技术，提高了半导体装置的可靠性。 在半导体芯片的主表面上形成的接合焊盘为矩形，并且在每个接合焊盘上的保护膜中形成开口，使得保护膜在每个接合的引线接合区域中的重叠宽度 衬垫比每个焊盘的探针区域中的保护膜的重叠宽度宽。