公开(公告)号：US20220123100A1

公开(公告)日：2022-04-21

申请号：US17500313

申请日：2021-10-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akira MITSUIKI

IPC: H01L49/02 ,  H01L27/01 ,  H01L21/306

Abstract: Reliability of a semiconductor device is improved, An interlayer insulating film and a pair of conductive layers that separate from each other through the interlayer insulating film are formed on a semiconductor substrate SUB. In this case, a position of each upper surface of the pair of conductive layers is different from a position of an upper surface of the interlayer insulating film, and an insulating film is formed between each upper surface of the pair of conductive layers and the upper surface of the interlayer insulating film. The insulating film has an incline surface that inclines with respect to each upper surface of the pair of conductive layers and die interlayer insulating film. A resistive element is connected to each of the pair of conductive layers, and is formed along the incline surface so as to cover the insulating film.

公开(公告)号：US20240162137A1

公开(公告)日：2024-05-16

申请号：US18510635

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Yuki SUGIYAMA ,  Eiji HIRAIWA ,  Akira MITSUIKI

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H01L28/60

Abstract: A manufacturing method of a semiconductor device includes: depositing a first conductor film, a dielectric film, and a second conductor film in this order in a MIM region and a wiring region; selectively removing the second conductor film, thereby forming an upper electrode of a capacitor element from the second conductor film; selectively removing the exposed dielectric film, thereby exposing the first conductor film in the wiring region and forming a dielectric layer having a flange portion remaining so as to protrude outward from a region under the upper electrode in the MIM region; and selectively removing the first conductor film, thereby forming a lower electrode of the capacitor element from the first conductor film and forming a wiring pattern from the first conductor film of which the upper surface is exposed in the wiring region.

公开(公告)号：US20160247931A1

公开(公告)日：2016-08-25

申请号：US15047732

申请日：2016-02-19

Applicant: Renesas Electronics Corporation

Inventor： Akira MITSUIKI

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L29/40117 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, a silicon film, for the memory gate electrode of a memory cell in a nonvolatile memory is formed via an insulating film so as to cover the control gate electrode of the memory cell. After the silicon film and the insulating film are removed from a peripheral circuit region, a silicon film for the gate electrode of a MISFET is formed over the silicon film over a memory cell region of the semiconductor substrate and over the peripheral circuit region thereof. After the silicon film is patterned to form a gate electrode over the peripheral circuit region, the insulating film is removed from the memory cell region. Then, over the silicon film over the memory cell region, an oxide film is formed. Subsequently, the oxide film, and, the silicon film over the silicon film over the memory cell region are etched back to form the memory gate electrode adjacent to the control gate electrode via the insulating film.

Abstract translation: 半导体器件的可靠性得到改善。 在半导体基板上，通过绝缘膜形成用于非易失性存储器中的存储单元的存储栅电极的硅膜，以覆盖存储单元的控制栅电极。 在从外围电路区域去除硅膜和绝缘膜之后，在半导体衬底的存储单元区域上并在其外围电路区域上形成用于MISFET的栅电极的硅膜。 在硅膜被图案化以在外围电路区域上形成栅极电极之后，从存储单元区域去除绝缘膜。 然后，在存储单元区域上方的硅膜上形成氧化膜。 随后，氧化膜以及存储单元区域上的硅膜上的硅膜被回蚀刻，以经由绝缘膜形成与控制栅电极相邻的存储栅电极。

公开(公告)号：US20160056233A1

公开(公告)日：2016-02-25

申请号：US14818516

申请日：2015-08-05

Applicant: Renesas Electronics Corporation

Inventor： Akira MITSUIKI ,  Tomoo NAKAYAMA ,  Shigeaki SHIMIZU ,  Hiroyuki OKUAKI

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/311 ,  H01L29/78 ,  H01L21/762 ,  H01L21/32

CPC classification number: H01L27/088 ,  H01L21/3083 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823456 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7835

Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.

Abstract translation: 抑制了凹部附近的电场集中。 栅极绝缘膜设置在其上具有漏极区域和第一凹部的衬底上。 第一凹部位于栅极绝缘膜和漏极区之间，并且填充有绝缘膜。 绝缘膜在靠近栅极绝缘膜的一侧具有第二凹部。 由第一凹部的内侧面和基板的表面限定的角度在靠近栅极绝缘膜的漏极区域的一侧为圆形。