公开(公告)号：US09558967B2

公开(公告)日：2017-01-31

申请号：US14928780

申请日：2015-10-30

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Takafumi Kuramoto ,  Risho Koh

IPC: H01L25/00 ,  H01L21/56 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L23/31 ,  H01L23/495 ,  H01L23/58

CPC classification number: H01L21/56 ,  H01L21/02164 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/562 ,  H01L23/564 ,  H01L23/58 ,  H01L28/10 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.

Abstract translation: 通过防止两个彼此面对的半导体芯片之间的电介质击穿，可以提高半导体器件的可靠性。 在制造第一和第二半导体芯片期间，执行绝缘膜的上表面的平坦化处理。 然后，第一半导体芯片和第二半导体芯片通过绝缘片堆叠，其中第一和第二半导体芯片的各个绝缘膜彼此面对，使得第一和第二半导体芯片的各个线圈彼此磁耦合。

公开(公告)号：US20180181696A1

公开(公告)日：2018-06-28

申请号：US15832256

申请日：2017-12-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Risho Koh ,  Mitsuru Miyamori ,  Katsumi Tsuneno

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: According to an embodiment, element models include a first transistor model, a second transistor model, and a variable resistor model. The first transistor model simulates a characteristic of a selection gate transistor whose channel resistance is changed by a selection gate voltage applied to a selection gate. The second transistor model simulates a characteristic of a memory gate transistor whose channel resistance is changed by a memory gate voltage applied to a memory gate. The variable resistor model has a resistance value which is changed in accordance with the selection gate voltage and the memory gate voltage and which is set to correspond to a gap region formed in a lower part of an insulating film insulating between the selection gate and the memory gate. The variable resistor model is provided between the first transistor model and the second transistor model.

公开(公告)号：US20160197066A1

公开(公告)日：2016-07-07

申请号：US14928780

申请日：2015-10-30

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Takafumi Kuramoto ,  Risho Koh

IPC: H01L25/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/02164 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/562 ,  H01L23/564 ,  H01L23/58 ,  H01L28/10 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.

Abstract translation: 通过防止两个彼此面对的半导体芯片之间的电介质击穿，可以提高半导体器件的可靠性。 在制造第一和第二半导体芯片期间，执行绝缘膜的上表面的平坦化处理。 然后，第一半导体芯片和第二半导体芯片通过绝缘片堆叠，其中第一和第二半导体芯片的各个绝缘膜彼此面对，使得第一和第二半导体芯片的各个线圈彼此磁耦合。