公开(公告)号：US10446543B2

公开(公告)日：2019-10-15

申请号：US15796816

申请日：2017-10-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Takafumi Kuramoto ,  Yasutaka Nakashiba

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/94 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L29/66 ,  H01L29/93 ,  H01L23/485

Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.

公开(公告)号：US10103773B2

公开(公告)日：2018-10-16

申请号：US15617738

申请日：2017-06-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Uchida ,  Takafumi Kuramoto

IPC: H04B1/44 ,  H01L49/02 ,  H01L23/58 ,  H01L23/528 ,  H01L23/552 ,  H03F3/195 ,  H01L27/06 ,  H03B5/12 ,  H01L23/522 ,  H03F3/213 ,  H04B5/00

Abstract: A semiconductor device and a communication circuit capable of reducing the effect of a noise generated in an inductor are provided. A semiconductor device according to an embodiment includes a substrate, a first circuit disposed in a first area of the substrate, a second circuit disposed in a second area of the substrate, the second circuit being configured to operate selectively with the first circuit, a first inductor disposed in the second area and connected to the first circuit, and a second inductor disposed in the first area and connected to the second circuit.

公开(公告)号：US09875962B2

公开(公告)日：2018-01-23

申请号：US15456976

申请日：2017-03-13

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida ,  Kazunori Go ,  Hiroshi Oe ,  Noriko Yoshikawa

IPC: G01R33/06 ,  H01L23/522 ,  H01F27/28 ,  H01L49/02 ,  H01L23/528 ,  G01R31/26

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.

公开(公告)号：US09558967B2

公开(公告)日：2017-01-31

申请号：US14928780

申请日：2015-10-30

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Takafumi Kuramoto ,  Risho Koh

IPC: H01L25/00 ,  H01L21/56 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L23/31 ,  H01L23/495 ,  H01L23/58

CPC classification number: H01L21/56 ,  H01L21/02164 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/562 ,  H01L23/564 ,  H01L23/58 ,  H01L28/10 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.

Abstract translation: 通过防止两个彼此面对的半导体芯片之间的电介质击穿，可以提高半导体器件的可靠性。 在制造第一和第二半导体芯片期间，执行绝缘膜的上表面的平坦化处理。 然后，第一半导体芯片和第二半导体芯片通过绝缘片堆叠，其中第一和第二半导体芯片的各个绝缘膜彼此面对，使得第一和第二半导体芯片的各个线圈彼此磁耦合。

公开(公告)号：US09529022B2

公开(公告)日：2016-12-27

申请号：US14477538

申请日：2014-09-04

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida

IPC: G01R1/20 ,  G01R19/00 ,  G01R15/18

CPC classification number: G01R19/0092 ,  G01R1/203 ,  G01R15/181

Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.

Abstract translation: 本发明以更低的成本提供传感器装置。 传感器装置包括印刷电路板，第一端子，第二端子，互连线和半导体器件。 第一端子和第二端子设置在印刷电路板上并耦合到电力线。 第二端子相对于第一端子耦合到电力线的下游部分。 互连线布置在印刷电路板上以将第一端子和第二端子彼此耦合。 换句话说，互连线并联耦合到电力线。 半导体器件安装在印刷电路板上，并且包括形成在互连层中的互连层和电感器。

公开(公告)号：US09257400B2

公开(公告)日：2016-02-09

申请号：US14487762

申请日：2014-09-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Kenji Nishikawa ,  Masato Kanno ,  Mika Yonezawa ,  Shunichi Kaeriyama ,  Toshinori Kiyohara

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/495 ,  H01L23/522 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L28/10 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/29034 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32135 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48249 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/743 ,  H01L2224/75745 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract translation: 半导体器件具有芯片安装部分，第一半导体芯片和第二半导体芯片。 第一半导体芯片沿其第一主平面面向芯片安装部分的方向安装在芯片安装部分上。 第二半导体芯片的一部分在其第三主平面面向第一半导体芯片的方向上安装在芯片安装部分上。 元件安装部分具有凹口部分。 第二半导体芯片的一部分与切口部分重叠。 在与切口部重叠的第二半导体芯片的第三主平面的区域中，设置有第二电极焊盘。

公开(公告)号：US09245840B2

公开(公告)日：2016-01-26

申请号：US14527293

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Takasuke Hashimoto ,  Shinichi Uchida ,  Yasutaka Nakashiba ,  Takatsugu Nemoto

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/58 ,  H05K9/00

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L2924/0002 ,  H05K9/00 ,  H01L2924/00

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor.An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract translation: 为了抑制由电感器引起的噪声泄漏到外部，并且还被配置为使得磁场强度变化到达电感器。 电感器在平面视图中围绕内部电路，并且还与内部电路电连接。 电感器的上侧由上屏蔽部分覆盖，电感器的下侧由下屏蔽部分覆盖。 上部屏蔽部分通过使用多层布线层形成。 上部屏蔽部分具有多个第一开口。 第一个开口在平面视图中与电感器重叠。

公开(公告)号：US08686540B2

公开(公告)日：2014-04-01

申请号：US13891260

申请日：2013-05-10

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L29/00 ,  H01L21/8238

CPC classification number: H01L23/5283 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/585 ,  H01L2223/6611 ,  H01L2924/0002 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, a wiring layer provided over the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring. In a plan view, the wiring layer includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region. The high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region. The plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively. An average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region.

Abstract translation: 半导体器件包括半导体衬底，设置在半导体衬底上的布线层，设置在布线层中的高频布线，以及设置在布线层中的与高频布线分开的多个虚设金属。 在平面图中，布线层包括高频布线附近区域和围绕高频布线附近区域的外部区域。 高频配线附近区域包括由高频配线的外缘包围的第一区域和围绕第一区域的第二区域。 多个虚设金属分散配置在高频配线附近区域和外部区域。 高频配线附近区域的虚拟金属间的平均间隔比外部区域宽。

公开(公告)号：US11756881B2

公开(公告)日：2023-09-12

申请号：US17231623

申请日：2021-04-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba ,  Shinichi Kuwabara

IPC: H01L23/522 ,  H01F27/28 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01F27/2804 ,  H01L23/5226 ,  H01L24/48 ,  H01L2224/48137

Abstract: A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends.

公开(公告)号：US09589887B2

公开(公告)日：2017-03-07

申请号：US14863264

申请日：2015-09-23

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Kazuo Henmi

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L25/065 ,  H04B5/00 ,  H01F38/14 ,  H01L23/48 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06527 ,  H01L2924/13055 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014

Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.

Abstract translation: 在相对的两个半导体芯片之间防止介电击穿，以提高半导体器件的可靠性。 第一半导体芯片具有包括多个布线层的布线结构，在布线结构中形成的第一线圈和形成在布线结构上的绝缘膜。 第二半导体芯片具有包括多个布线层的布线结构，形成在布线结构上的第二线圈和形成在布线结构上的绝缘膜。 第一半导体芯片和第二半导体芯片通过绝缘片与第一半导体芯片的绝缘膜和第二半导体芯片的绝缘膜彼此面对而堆叠。 第一线圈和第二线圈彼此磁耦合。 然后，在第一和第二半导体芯片的每一个中，在最上层布线层形成布线和虚拟布线。