中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.026 seconds)

    System and method for optimized error correction in flash memory arrays
    1.
    发明授权
    System and method for optimized error correction in flash memory arrays 有权
    用于闪存阵列优化纠错的系统和方法

    公开(公告)号：US08261124B2

    公开(公告)日：2012-09-04

    申请号：US11963078

    申请日：2007-12-21

    Applicant: Richard Carmichael

    Inventor： Richard Carmichael

    IPC: G06F11/00 ,  G06F11/16

    CPC classification number: G06F11/1068

    Abstract: Systems and/or methods that facilitate that facilitate error correction of data stored in memory components, such as flash memory devices are presented. An optimized correction component can be used to break data into two or more data blocks. The optimized correction component can facilitated creating one or two redundancy blocks that can be associated with the data blocks, wherein data blocks and the redundancy blocks can be assembled into a data stripe that can be stored in three or more of the memory components. Upon retrieval of the data stripe, the optimal correction component, an error correction code (ECC) component or a combination thereof can correct data blocks that contain errors wherein the decision whether the optimized correction component or the error correction code (ECC) component corrects the errors can be based in part on a predetermined criteria.

    Abstract translation: 提出了便于促进存储在诸如闪存设备之类的存储器组件中的数据的纠错的系统和/或方法。 可以使用优化的校正组件将数据分解成两个或更多个数据块。 优化的校正组件可以促进创建可以与数据块相关联的一个或两个冗余块，其中数据块和冗余块可以被组合成可存储在三个或更多个存储器组件中的数据条带。 在检索数据条带时，最佳校正分量，纠错码（ECC）分量或其组合可以校正包含误差的数据块，其中判定优化校正分量或纠错码（ECC）分量是否校正 错误可以部分地基于预定标准。

    Clock encoded pre-fetch to access memory data in clustering network environment
    4.
    发明授权
    Clock encoded pre-fetch to access memory data in clustering network environment 有权
    时钟编码预取，以访问集群网络环境中的内存数据

    公开(公告)号：US07827359B2

    公开(公告)日：2010-11-02

    申请号：US11957027

    申请日：2007-12-14

    Applicant: Richard Carmichael

    Inventor： Richard Carmichael

    IPC: G06F13/00 ,  G06F9/26

    CPC classification number: G06F12/0862 ,  G06F2212/6028

    Abstract: Systems and/or methods that facilitate reading data from a memory component associated with a network are presented. A pre-fetch generation component generates a pre-fetch request based in part on a received read command. To facilitate a reduction in latency associated with transmitting the read command via an interconnect network component to which the memory component is connected, the pre-fetch request is transmitted directly to the memory component bypassing a portion of the interconnect network component. The memory component specified in the pre-fetch request receives the pre-fetch request and reads the data stored therein, and can store the read data in a buffer and/or transmit the read data to the requester via the interconnect network component, even though the read command has not yet reached the memory component. The read data is verified by comparison with the read command at a convergence point.

    Abstract translation: 提出了便于从与网络相关联的存储器组件读取数据的系统和/或方法。 部分取决于接收到的读取命令，预取生成组件生成预取请求。 为了便于与通过连接存储器组件的互连网络组件发送读取命令相关联的延迟的减少，预取请求直接发送到绕过互连网络组件的一部分的存储器组件。 在预取请求中指定的存储器组件接收预取请求并读取其中存储的数据，并且可以将读取的数据存储在缓冲器中和/或经由互连网络组件将读取的数据发送到请求者，即使 读命令尚未到达内存组件。 通过与收敛点处的读取命令进行比较来验证读取的数据。

    ERROR CORRECTION IN FLASH MEMORY ARRAY
    5.
    发明申请
    ERROR CORRECTION IN FLASH MEMORY ARRAY 有权
    闪存存储器阵列中的错误校正

    公开(公告)号：US20090164836A1

    公开(公告)日：2009-06-25

    申请号：US11963078

    申请日：2007-12-21

    Applicant: Richard Carmichael

    Inventor： Richard Carmichael

    IPC: G06F11/00

    CPC classification number: G06F11/1068

    Abstract: Systems and/or methods that facilitate that facilitate error correction of data stored in memory components, such as flash memory devices are presented. An optimized correction component can be used to break data into two or more data blocks. The optimized correction component can facilitated creating one or two redundancy blocks that can be associated with the data blocks, wherein data blocks and the redundancy blocks can be assembled into a data stripe that can be stored in three or more of the memory components. Upon retrieval of the data stripe, the optimal correction component, an error correction code (ECC) component or a combination thereof can correct data blocks that contain errors wherein the decision whether the optimized correction component or the error correction code (ECC) component corrects the errors can be based in part on a predetermined criteria.

    Abstract translation: 提出了便于促进存储在诸如闪存设备之类的存储器组件中的数据的纠错的系统和/或方法。 可以使用优化的校正组件将数据分解成两个或更多个数据块。 优化的校正组件可以促进创建可以与数据块相关联的一个或两个冗余块，其中数据块和冗余块可以被组合成可存储在三个或更多个存储器组件中的数据条带。 在检索数据条带时，最佳校正分量，纠错码（ECC）分量或其组合可以校正包含误差的数据块，其中判定优化校正分量或纠错码（ECC）分量是否校正 错误可以部分地基于预定标准。

    Race condition prevention
    6.
    发明申请
    Race condition prevention 有权
    种族状况预防

    公开(公告)号：US20060143331A1

    公开(公告)日：2006-06-29

    申请号：US11013033

    申请日：2004-12-14

    Applicant: Nathan Marushak ,  Roger Jeppsen ,  Richard Beckett ,  Devicharan Devidas ,  Richard Carmichael

    Inventor： Nathan Marushak ,  Roger Jeppsen ,  Richard Beckett ,  Devicharan Devidas ,  Richard Carmichael

    IPC: G06F3/06

    CPC classification number: G06F13/385 ,  H04L1/0061 ,  H04L1/1874 ,  H04L1/1887 ,  H04L2001/0094

    Abstract: One embodiment of a method may include, in response, at least in part, to one or more received frames, generating an interrupt and preventing transmission of one or more other frames. The one or more received frames may indicate, at least in part, an error condition or a commencement of a data transfer. The method of this embodiment also may include, in response, at least in part, to the interrupt, executing one or more instructions. The one or more instructions, when executed, may optionally result in deleting the one or more other frames, and if the one or more received frames indicate, at least in part, the error condition, commencing recovery from the error condition. If the one or more received frames indicate, at least in part, the commencement of the data transfer, the method of the embodiment may include storing data associated with the data transfer.

    Abstract translation: 方法的一个实施例可以响应于至少部分地包括一个或多个接收的帧，产生中断并防止一个或多个其他帧的传输。 至少部分地，一个或多个接收到的帧可以指示错误状况或数据传送的开始。 该实施例的方法还可以响应于至少部分地包括执行一个或多个指令的中断。 一个或多个指令在执行时可以可选地导致删除一个或多个其他帧，并且如果一个或多个接收到的帧至少部分地指示错误状况，则从错误状态开始恢复。 如果一个或多个接收的帧至少部分地指示数据传输的开始，则该实施例的方法可以包括存储与数据传输相关联的数据。

    Condensate trap
    9.
    发明申请
    Condensate trap 审中-公开
    冷凝阱

    公开(公告)号：US20060108013A1

    公开(公告)日：2006-05-25

    申请号：US10541717

    申请日：2004-01-12

    Applicant: Richard Carmichael

    Inventor： Richard Carmichael

    IPC: F15C1/16

    CPC classification number: F16T1/34 ,  Y10T137/2093

    Abstract: A steam trap (1) is provided comprising a chamber (8) having a substantially cylindrical sidewall, an inlet 20 provided towards the upper end of the sidewall, and an escape aperture (16) provided at its base. The inlet (20) introduces the fluid into the chamber (8) in a manner to promote a rotational flow of the fluid in the chamber (8), so as to create a low pressure location upstream of the escape aperture (16) to restrict the discharge rate of the aperture (16).

    Abstract translation: 提供一种蒸汽疏水阀（1），其包括具有基本圆柱形侧壁的腔室（8），朝向侧壁的上端设置的入口20和设置在其底部的排出口（16）。 入口（20）以促进腔室（8）中的流体的旋转流动的方式将流体引入腔室（8）中，以便在排出口（16）的上游产生低压位置，以限制 孔径（16）的排出速率。

    Integrated circuit capable of pre-descrambling a portion of a frame
    10.
    发明申请
    Integrated circuit capable of pre-descrambling a portion of a frame 审中-公开
    能够对帧的一部分进行预解扰的集成电路

    公开(公告)号：US20060088163A1

    公开(公告)日：2006-04-27

    申请号：US10972841

    申请日：2004-10-25

    Applicant: Richard Carmichael

    Inventor： Richard Carmichael

    IPC: H04N7/167

    CPC classification number: H04N21/44055 ,  H04N7/1675

    Abstract: A method according to one embodiment may include receiving a frame comprising scrambled data, identifying a portion of the scrambled data, descrambling the portion to obtain descrambled data associated with the portion; and evaluating the descrambled data and providing a result of the evaluating operation before completion of descrambling of all of the scrambled data of the frame. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

    Abstract translation: 根据一个实施例的方法可以包括：接收包括加扰数据的帧，识别加扰数据的一部分，对该部分进行解扰，以获得与该部分相关联的解扰数据; 以及在对所述帧的所有加扰数据进行解扰的完成之前评估所述解扰数据并提供所述评估操作的结果。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

Patent Agency Ranking