公开(公告)号：US08896048B1

公开(公告)日：2014-11-25

申请号：US10861581

申请日：2004-06-04

申请人： Richard Fastow ,  Zhigang Wang ,  Yue-Song He ,  Kazuhiro Mizutani ,  Pavel Fastenko

发明人： Richard Fastow ,  Zhigang Wang ,  Yue-Song He ,  Kazuhiro Mizutani ,  Pavel Fastenko

IPC分类号： H01L29/76

CPC分类号： H01L29/66659 ,  H01L29/66825 ,  H01L29/7881

摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

摘要翻译： 本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极 地区。 源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。 漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

公开(公告)号：US06773990B1

公开(公告)日：2004-08-10

申请号：US10429150

申请日：2003-05-03

申请人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

发明人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

IPC分类号： H10L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

摘要翻译： 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间 区域，其中沟槽限定衬底中的侧壁。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方 地区。

公开(公告)号：US06963106B1

公开(公告)日：2005-11-08

申请号：US10839626

申请日：2004-05-04

申请人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

发明人： Richard Fastow ,  Yue-Song He ,  Kazuhiro Mizutani ,  Timothy Thurgate

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

摘要翻译： 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间 区域，其中沟槽限定衬底中的侧壁。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。 该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方 地区。

公开(公告)号：US07151028B1

公开(公告)日：2006-12-19

申请号：US10981174

申请日：2004-11-04

申请人： Shenqing Fang ,  Rinji Sugino ,  Kuo-Tung Chang ,  Zhigang Wang ,  Kazuhiro Mizutani ,  Pavel Fastenko

发明人： Shenqing Fang ,  Rinji Sugino ,  Kuo-Tung Chang ,  Zhigang Wang ,  Kazuhiro Mizutani ,  Pavel Fastenko

IPC分类号： H01L21/26

CPC分类号： H01L29/66636 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/7881

摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.

摘要翻译： 根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成邻近层叠栅极结构的源极侧壁的第一间隔物的步骤，其中堆叠的栅极结构位于 基质。 该方法还包括在衬底的源区中形成与第一间隔物相邻的高能注入掺杂区。 该方法还包括在源极区域中形成凹部，其中凹部的侧壁位于与浮动栅极存储单元的源极相邻处，并且其中形成凹槽包括移除第一间隔物。 该方法还包括形成邻近层叠栅极结构的源极侧壁的第二间隔物，其中第二间隔物延伸到凹部的底部，并且其中第二间隔物包括等离子体生长的氧化物。

公开(公告)号：US07851306B2

公开(公告)日：2010-12-14

申请号：US12327641

申请日：2008-12-03

申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

摘要翻译： 本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。 植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。 源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。 源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。 与漏极触点排共线的源触点的布置允许直线字线形成。

公开(公告)号：US07488657B2

公开(公告)日：2009-02-10

申请号：US11155707

申请日：2005-06-17

申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

摘要翻译： 本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。 植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。 源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。 源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。 与漏极触点排共线的源触点的布置允许直线字线形成。

公开(公告)号：US20060286750A1

公开(公告)日：2006-12-21

申请号：US11155707

申请日：2005-06-17

申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

公开(公告)号：US08237210B1

公开(公告)日：2012-08-07

申请号：US11349562

申请日：2006-02-08

申请人： Zhigang Wang ,  Kazuhiro Mizutani ,  Richard Fastow

发明人： Zhigang Wang ,  Kazuhiro Mizutani ,  Richard Fastow

IPC分类号： H01L29/76

CPC分类号： G11C15/00

摘要： A semiconductor apparatus is presented that includes an array of memory cells. The memory cells are arranged in rows and columns. Non-intersecting shallow trench isolation regions isolate the columns of memory cells. Also included is at least one source region that is isolated between an adjoining pair of the non-intersecting shallow trench isolation regions and isolated from a drain region. The source region is coupled to source lines in the array of memory cells. A contact couples a select plurality of the columns of memory cells, the select plurality functioning as a single content addressable memory cell.

摘要翻译： 提出了一种包括存储单元阵列的半导体装置。 存储单元以行和列排列。 不相交的浅沟槽隔离区域隔离存储单元的列。 还包括至少一个源极区域，其隔离在相邻的一对不相交的浅沟槽隔离区域之间并与漏极区域隔离。 源极区域耦合到存储器单元阵列中的源极线。 一个触点耦合选择的多个存储单元列，所述选择多个功能用作单个内容可寻址存储单元。

公开(公告)号：US07029975B1

公开(公告)日：2006-04-18

申请号：US10839561

申请日：2004-05-04

申请人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

发明人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/513

摘要： A method and apparatus for coupling to a source line is disclosed. A semiconductor structure having an array of memory cells arranged in rows and columns is described. The array of memory cells includes a source region that is implanted with n-type dopants isolated between an adjoining pair of the non-intersecting STI regions and isolated from a drain region during the implantation. A source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells and the source contact is coupled to the source region for providing electrical coupling with a plurality of source lines. The isolating of the implanted source region from the drain region during the implanting enables coupling of the source contact to the source lines while maintaining the n-type dopants between the STI regions and avoiding lateral diffusion to a bit-line.

摘要翻译： 公开了一种用于耦合到源极线的方法和装置。 描述了具有排列成行和列的存储单元阵列的半导体结构。 存储单元阵列包括源区域，其注入在相邻的一对不相交的STI区域之间隔离并在植入期间与漏区隔离的n型掺杂剂。 源极触点沿着一排漏极触点排列，其被连接到一行存储器单元的漏极区域，并且源极触点耦合到源极区域以提供与多个源极线的电耦合。 在植入期间将注入的源极区域与漏极区域隔离使得能够将源极接触耦合到源极线，同时保持STI区域之间的n型掺杂剂并且避免横向扩散到位线。

公开(公告)号：US07301193B2

公开(公告)日：2007-11-27

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。