公开(公告)号：US07301193B2

公开(公告)日：2007-11-27

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

公开(公告)号：US20050164450A1

公开(公告)日：2005-07-28

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/74 ,  H01L29/417 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

公开(公告)号：US06808992B1

公开(公告)日：2004-10-26

申请号：US10150240

申请日：2002-05-15

申请人： Kelwin Ko ,  Shenqing Fang ,  Angela T. Hui ,  Hiroyuki Kinoshita ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Kelwin Ko ,  Shenqing Fang ,  Angela T. Hui ,  Hiroyuki Kinoshita ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L29/6656

摘要： A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.

摘要翻译： 描述了一种用于提供半导体器件的方法和系统。 半导体器件包括衬底，芯和周边。 芯包括具有第一多个边缘的多个核心栅极叠层，而周边具有多个具有第二多个边缘的外围栅极堆叠。 该方法和系统包括提供多个芯间隔件，多个外围间隔件，多个芯源和多个导电区域。 芯间隔件位于第一多个边缘处并且具有厚度。 外围间隔件位于第二多个边缘处并且具有大于第一厚度的第二厚度。 核心源位于多个核心门堆栈之间。 导电区域在多个核心源上。 该方法允许不同厚度的间隔件形成在芯部和周边中，使得间隔件可以根据芯部和周边的不同要求进行调整。

公开(公告)号：US06974995B1

公开(公告)日：2005-12-13

申请号：US10032757

申请日：2001-12-27

申请人： Angela Hui ,  Shenqing Fang ,  Hiroyuki Kinoshita ,  Kelwin Ko ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa ,  Chi Chang

发明人： Angela Hui ,  Shenqing Fang ,  Hiroyuki Kinoshita ,  Kelwin Ko ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa ,  Chi Chang

IPC分类号： H01L21/8238 ,  H01L21/8239 ,  H01L27/105 ,  H01L29/772

CPC分类号： H01L21/823842 ,  H01L27/1052

摘要： A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.

摘要翻译： 描述了一种用于提供半导体器件的方法和系统。 半导体包括芯和外围。 所述方法和系统包括在芯中提供多个核心堆栈，在核心中提供多个源极和在周边的多个外围栅极叠层。 多个核心栅堆叠中的每一个包括第一多晶硅栅极和位于第一多晶硅栅极上方的WSi层。 多个源位于多个核心栅极叠层的一部分之间。 多个外围栅极堆叠中的每一个在第二多晶硅栅极上包括第二多晶硅栅极和CoSi层。

公开(公告)号：US07851306B2

公开(公告)日：2010-12-14

申请号：US12327641

申请日：2008-12-03

申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

摘要翻译： 本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。 植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。 源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。 源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。 与漏极触点排共线的源触点的布置允许直线字线形成。

公开(公告)号：US07488657B2

公开(公告)日：2009-02-10

申请号：US11155707

申请日：2005-06-17

申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

摘要翻译： 本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。 植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。 源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。 源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。 与漏极触点排共线的源触点的布置允许直线字线形成。

公开(公告)号：US20060286750A1

公开(公告)日：2006-12-21

申请号：US11155707

申请日：2005-06-17

申请人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

发明人： Shenqing Fang ,  Hiroyuki Ogawa ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani ,  Zhigang Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

公开(公告)号：US07226839B1

公开(公告)日：2007-06-05

申请号：US10861575

申请日：2004-06-04

申请人： King Wai Kelwin Ko ,  Hiroyuki Kinoshita ,  Hiroyuki Ogawa ,  Yu Sun

发明人： King Wai Kelwin Ko ,  Hiroyuki Kinoshita ,  Hiroyuki Ogawa ,  Yu Sun

IPC分类号： H01L21/8234

CPC分类号： H01L27/105 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  Y10S438/926

摘要： A method and system for improving the topography of a memory array is disclosed. In one embodiment, a dummy bitline is formed over a field oxide region at an interface between a memory array and interface circuitry. In addition, a poly-2 layer is applied above the dummy bitline on the field oxide region wherein the utilization of the field oxide region for placement of the dummy bitline provides a uniform surface between an actual bitline and the periphery of the memory array. Furthermore, a landing pad is formed at the end of the dummy bitline on the field oxide region, wherein the dummy bitline does not cause erroneous operation of the landing pad.

摘要翻译： 公开了一种用于改善存储器阵列的形貌的方法和系统。 在一个实施例中，在存储器阵列和接口电路之间的接口处的场氧化物区域上形成虚拟位线。 此外，在场氧化物区域上的虚拟位线之上施加多晶硅层2，其中用于放置虚拟位线的场氧化物区域的利用在实际位线和存储器阵列的外围之间提供均匀的表面。 此外，在场氧化物区域上的虚拟位线的末端形成着陆焊盘，其中虚拟位线不会引起着陆焊盘的错误操作。

公开(公告)号：US08658496B2

公开(公告)日：2014-02-25

申请号：US13617291

申请日：2012-09-14

申请人： Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

发明人： Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

IPC分类号： H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

摘要翻译： 提供存储器件和制造存储器件的方法。 在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层， 保形膜形成在存储器件的表面上。

公开(公告)号：US08319266B1

公开(公告)日：2012-11-27

申请号：US11008240

申请日：2004-12-10

申请人： Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

发明人： Hiroyuki Kinoshita ,  Angela Hui ,  Hsiao-Han Thio ,  Kuo-Tung Chang ,  Minh Van Ngo ,  Hiroyuki Ogawa

IPC分类号： H01L29/788

CPC分类号： H01L21/0217 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

摘要翻译： 提供存储器件和制造存储器件的方法。 在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层， 保形膜形成在存储器件的表面上。