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1.发明申请PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES 有权可编程SRAM SRAM源开发方案可供选择的SRAM供电电压组公开(公告)号：US20080198678A1
公开(公告)日：2008-08-21
申请号：US12029366
申请日：2008-02-11
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147 , G11C5/148 , G11C11/41 , G11C11/413 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.
摘要翻译： 存储电路具有高电压和低电压电源节点。 根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。 如果处于主动读/写模式，则选择性地施加第一组电压。 相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。 所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压 所述第一组电压通过多个高偏移电压中的所选择的一个。 偏移电压由选择性有效的基于二极管的电路提供。 选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。
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公开(公告)号：US20080198679A1
公开(公告)日：2008-08-21
申请号：US12030463
申请日：2008-02-13
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C11/412 , G11C11/413
摘要： A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.
摘要翻译： 电路包括具有高电压供应节点和低电压供应节点的存储单元。 功率复用电路被提供用于根据小区的当前操作模式选择性地将第一组电压和第二组电压中的一个应用于小区的高电压和低电压供应节点。 如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。 相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。 第二组电压偏离第一组电压。 更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。 单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。 阵列可以包括包括许多块或部分的整个存储器装置内的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。
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公开(公告)号：US08482964B2
公开(公告)日：2013-07-09
申请号：US12645039
申请日：2009-12-22
申请人： Kevin K. Walsh , Paul F. Gerrish , Larry E. Tyler , Mark A. Lysinger , David C. McClure , Francois Jacquet
发明人： Kevin K. Walsh , Paul F. Gerrish , Larry E. Tyler , Mark A. Lysinger , David C. McClure , Francois Jacquet
IPC分类号： G11C11/00
CPC分类号： G11C5/14 , G11C5/147 , G11C11/417
摘要： An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.
摘要翻译： 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。
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公开(公告)号：US20100165709A1
公开(公告)日：2010-07-01
申请号：US12645039
申请日：2009-12-22
申请人： Kevin K. Walsh , Paul F. Gerrish , Larry E. Tyler , Mark A. Lysinger , David C. McClure , Francois Jacquet
发明人： Kevin K. Walsh , Paul F. Gerrish , Larry E. Tyler , Mark A. Lysinger , David C. McClure , Francois Jacquet
CPC分类号： G11C5/14 , G11C5/147 , G11C11/417
摘要： An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.
摘要翻译： 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。
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公开(公告)号：US5267210A
公开(公告)日：1993-11-30
申请号：US25894
申请日：1993-03-03
申请人： David C. McClure , Mark A. Lysinger
发明人： David C. McClure , Mark A. Lysinger
IPC分类号： G11C7/10 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/40
CPC分类号： G11C11/412 , G11C7/1048 , G11C7/12 , G11C7/20
摘要： A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.
摘要翻译： 具有多个I / O的静态随机存取存储器包括存储器单元（42）的存储器阵列（10），所述存储器单元（42）具有作为相关I / O的函数可选择地清零的列。 这些列以成对（34）排列，成对（34）中的每个列与相同的I / O相关联。 在线路（28）上输入清除信号并由驱动器（30）驱动。 清除信号仅与与选择的I / O相关联的对（34）相关联。 与未选择的I / O相关联的其余存储单元列不会被清除。
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公开(公告)号：US4974241A
公开(公告)日：1990-11-27
申请号：US332290
申请日：1989-03-31
申请人： David C. McClure , Mark A. Lysinger
发明人： David C. McClure , Mark A. Lysinger
CPC分类号： H04J3/0626
摘要： The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.
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公开(公告)号：US5450019A
公开(公告)日：1995-09-12
申请号：US185650
申请日：1994-01-26
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.
摘要翻译： 公开了一种推挽输出驱动器电路，其包括用于控制驱动器晶体管的栅极以在周期开始时实现输出端子的预充电的控制电路。 预充电在每个周期开始时启动，例如由地址转换指示。 存储输出端的先前数据状态，并且通过启用具有滞后的门控电平检测器（例如施密特触发器）来驱动存储的先前数据状态的驱动晶体管，使相对的驱动器晶体管成为可能。 驱动存储的先前数据状态的晶体管被禁用，从而排除了预充电期间的振荡。 门控施密特触发器每个接收输出端子的电压，并且在使能时，接通将输出端子耦合到驱动晶体管的栅极的晶体管。 当输出端子达到中间电压时，施密特触发器也可以控制预充电，从而由于滞后特性使振荡最小化。 输出端子连接到预充电驱动晶体管的栅极有助于在预充电期间消除过冲。
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公开(公告)号：US07623405B2
公开(公告)日：2009-11-24
申请号：US12030463
申请日：2008-02-13
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C11/412 , G11C11/413
摘要： A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can include a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.
摘要翻译： 电路包括具有高电压供应节点和低电压供应节点的存储单元。 功率复用电路被包括以根据小区的当前操作模式来选择性地将第一组电压和第二组电压中的一个应用于小区的高电压和低电压供应节点。 如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。 相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。 第二组电压偏离第一组电压。 更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。 单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。 阵列可以包括包括许多块或部分在内的整个存储器件中的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。
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9.发明授权Circuitry and methodology to test single bit failures of integrated circuit memory devices 失效用于测试集成电路存储器件单位故障的电路和方法
公开(公告)号：US5633828A
公开(公告)日：1997-05-27
申请号：US519075
申请日：1995-08-24
摘要： According to the present invention, a structure and method provides for single bit failures of an integrated circuit memory device to be analyzed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads. According to the structure of the present invention, bitline load devices of the integrated circuit memory device are controlled by a test mode signal, the state of which determines when the test mode will be entered. These bitline load devices are connected to the bitlines true and complement which in turn are connected to the memory cell. Select devices, such as column select transistors, are connected to the bitline true and bitline complement; they are also connected to driver circuitry by a bus, such as a write bus, a read bus or a write/read bus. The driver circuitry is supplied with supply voltages as well as data signals. Further, a buffer circuit allows bitlines true and bitlines complement not associated with the single bit being tested to be pulled to a logic low level. A dummy structure also provides the opportunity to directly monitor the bitlines of the integrated circuit memory device without the need for microprobing.
摘要翻译： 根据本发明，结构和方法提供要分析的集成电路存储器件的单位故障。 根据用于分析集成电路存储器件的单位故障的方法，输入测试模式，集成电路存储器件的位线负载器件被截止，选择集成电路存储器件的单位，器件 被放置在写入模式中，然后将多个位线true和不与单个位相关联的集成电路存储器件的多个位线补码设置为低逻辑电平，与单个位相关联的位线真和位线补码 位连接到连接到测试焊盘的电源总线和电源补充总线。 最后，可以在测试焊盘上监视单个位的电气特性。 根据本发明的结构，集成电路存储器件的位线负载装置由测试模式信号控制，其状态决定了何时进入测试模式。 这些位线负载装置连接到位线和真正的补码，而补码又连接到存储单元。 选择器件，如列选择晶体管，连接到位线真和位线补码; 它们也通过总线连接到驱动器电路，例如写总线，读总线或写/读总线。 驱动器电路提供电源电压以及数据信号。 此外，缓冲电路允许位线为真，并且与待测试的单个位相关联的位线补码被拉至逻辑低电平。 虚拟结构还提供了直接监视集成电路存储器件的位线的机会，而不需要微阵列。
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公开(公告)号：US5005158A
公开(公告)日：1991-04-02
申请号：US464219
申请日：1990-01-12
申请人： David C. McClure , Mark A. Lysinger
发明人： David C. McClure , Mark A. Lysinger
摘要： A fault tolerant sequential memory includes primary and redundant memory rows (or columns) and primary and redundant shift registers. The redundant memory rows (or columns) and redundant shift registers are formed at the end of the serial chain. Each shift register of each primary and redundant memory block is interconnected with an independent, separately programmable multiplexer logic circuit. Each multiplexer logic circuit includes an independently programmable repair buffer for logically bypassing a defective primary memory block and associated shift registers within the primary memory array. Each redundant memory block includes a multiplexer logic circuit having an independently programmable repair buffer for logically enabling a redundant memory block and shift register at the end of the serial chain. Consequently, a faulty memory block, including its shift register and memory row (or column) is bypassed and is effectively removed from the shifting sequence. The redundant memory block, including a redundant shift register and a redundant row (or column), is inserted at the end of the shift register chain by opening a programmable fuse element.
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