摘要:
The present invention describes a communications system having a first link partner and a second link partner that are connected by a communications link having at least four pairs of conductors. According to IEEE Standard 802.3 (e.g. Ethernet) for 1000Base-T, a data link is maintained (in a period absent data transmission) by sending idle signals over four pairs of conductors of the cable to maintain a logical connection. This idle signal scheme is replaced with an alternate idle signaling scheme that uses only two pairs of conductors to maintain a logical connection and therefore can operate with using lower power. The other two pairs of conductors of the four pairs of conductors are unused to maintain a logical connection absent data transfer, and therefore can be used to implement a Suspend Mode of operation. During Suspend Mode, the physical layer of each link partner powers down unnecessary circuitry so as to operate in a low power environment. To initiate the Suspend Mode, idle signals are sent on one of the un-used pairs of the conductors mentioned above. To exit Suspend mode, idle signals are sent on respective conductors simultaneously.
摘要:
The present invention describes a communications system having a first link partner and a second link partner that are connected by a communications link having at least four pairs of conductors. According to IEEE Standard 802.3 (e.g. Ethernet) for 1000Base-T, a data link is maintained (in a period absent data transmission) by sending idle signals over four pairs of conductors of the cable to maintain a logical connection. This idle signal scheme is replaced with an alternate idle signaling scheme that uses only two pairs of conductors to maintain a logical connection and therefore can operate with using lower power. The other two pairs of conductors of the four pairs of conductors are unused to maintain a logical connection absent data transfer, and therefore can be used to implement a Suspend Mode of operation. During Suspend Mode, the physical layer of each link partner powers down unnecessary circuitry so as to operate in a low power environment. To initiate the Suspend Mode, idle signals are sent on one of the un-used pairs of the conductors mentioned above. To exit Suspend mode, idle signals are sent on respective conductors simultaneously.
摘要:
The present invention describes a communications system having a first link partner and a second link partner that are connected by a communications link having at least four pairs of conductors. According to IEEE Standard 802.3 (e.g. Ethernet) for 1000Base-T, a data link is maintained (in a period absent data transmission) by sending idle signals over four pairs of conductors of the cable to maintain a logical connection. This idle signal scheme is replaced with an alternate idle signaling scheme that uses only two pairs of conductors to maintain a logical connection and therefore can operate with using lower power. The other two pairs of conductors of the four pairs of conductors are unused to maintain a logical connection absent data transfer, and therefore can be used to implement a Suspend Mode of operation. During Suspend Mode, the physical layer of each link partner powers down unnecessary circuitry so as to operate in a low power environment. To initiate the Suspend Mode, idle signals are sent on one of the un-used pairs of the conductors mentioned above. To exit Suspend mode, idle signals are sent on respective conductors simultaneously.
摘要:
Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.
摘要:
A power efficient and reduced electromagnetic interference (EMI) emissions multi-transmitter system for unshielded twisted pair (UTP) data communication applications. For each transmitter, digital transmit data is converted to a current-mode differential signal analog waveform by a digital-to-analog converter (DAC). The output current from each DAC is used to generate the required transmit voltage on the respective UTP line. Timing circuitry staggers the time base of each transmitter to reduce the aggregate EMI emissions of the multi-transmitter system.
摘要:
Aspects of the invention include determining or choosing any usable media pair from all existing media pairs of a first device. Any channel may be selected from all existing channels and the selected channel is chosen so that it is different from a general channel assignment corresponding to the determined usable media pair. The selected channel may be assigned to the media pair. A second device may be notified of the assigned channel which corresponds to the media pair chosen from all the media pairs. The second device may cross-connect a corresponding equivalent channel and media pair. The first and second device may be adapted to negotiate the assignment of the selected channel to any one of the media pairs. Alternatively, a particular channel and media pair assignment may be selected from a plurality of predetermined channel and media pair assignments and utilized by the first and second device.
摘要:
A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode. For a multi-transmitter system, timing circuitry staggers the time base of each transmitter to reduce the aggregate EMI emissions of the multi-transmitter system.
摘要:
Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.
摘要:
A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or voltage overshoot in the IC die and/or at a load that is connected to the IC die. The IC die can further include a line driver to provide a source current. A bias generator can be included to provide a bias current to the line driver. The bias generator can include a first current source coupled to an off-chip resistor and a second current source coupled to an on-chip resistor. An output voltage of the IC die can be adjusted by manipulating a trim control of the off-chip resistor and/or a trim control of the on-chip resistor.
摘要:
A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.