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1.发明授权公开(公告)号：US07262864B1
公开(公告)日：2007-08-28
申请号：US09897573
申请日：2001-07-02
CPC分类号： G01B11/24 , G03F7/70625
摘要： A test structure includes a first plurality of lines and a second plurality of lines intersecting the first plurality of lines. The first and second pluralities of lines defining a grid having openings. A method for determining grid dimensions includes providing a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings; illuminating at least a portion of the grid with a light source; measuring light reflected from the illuminated portion of the grid to generate a reflection profile; and determining a dimension of the grid based on the reflection profile. A metrology tool is adapted to receive a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the grid. The detector is adapted to measure light reflected from the illuminated portion of the grid to generate a reflection profile. The data processing unit is adapted to determine a dimension of the grid based on the reflection profile.
摘要翻译： 测试结构包括与第一组多行相交的第一多行和第二多行。 限定具有开口的网格的第一和第二多行线。 用于确定网格尺寸的方法包括提供具有测试结构的晶片，该测试结构包括限定具有开口的网格的多个相交线; 用光源照亮网格的至少一部分; 测量从所述格栅的被照亮部分反射的光以产生反射分布; 以及基于所述反射分布来确定所述网格的尺寸。 测量工具适于接收具有测试结构的晶片，该测试结构包括限定具有开口的格栅的多个相交线。 计量工具包括光源，检测器和数据处理单元。 光源适于照亮网格的至少一部分。 检测器适于测量从栅格的照明部分反射的光以产生反射分布。 数据处理单元适于基于反射分布来确定网格的尺寸。
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2.发明授权Method and apparatus for determining contact opening dimensions using scatterometry 失效使用散射法确定接触开口尺寸的方法和装置公开(公告)号：US06804014B1
公开(公告)日：2004-10-12
申请号：US09897576
申请日：2001-07-02
IPC分类号： G01B1114
CPC分类号： G03F7/70491 , G01B11/14 , G03F7/705 , G03F7/70558 , G03F7/70616 , G03F7/70625
摘要： A test structure includes a plurality of lines and a plurality of contact openings defined in the lines. A method for determining contact opening dimensions includes providing a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines; illuminating at least a portion of the contact openings with a light source; measuring light reflected from the illuminated portion of the contact openings to generate a reflection profile; and determining a dimension of the contact openings based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the contact openings. The detector is adapted to measure light reflected from the illuminated portion of the contact openings to generate a reflection profile. The data processing unit is adapted to determine a dimension of the contact openings based on the reflection profile.
摘要翻译： 测试结构包括多条线和在线中限定的多个接触开口。 用于确定接触开口尺寸的方法包括提供具有测试结构的晶片，该测试结构包括限定在所述线中的多条线和多个接触开口; 用光源照射至少一部分接触开口; 测量从接触开口的被照射部分反射的光以产生反射分布; 以及基于反射曲线确定接触开口的尺寸。 适于接收具有测试结构的测量工具的测量结构包括多条线和在该线中限定的多个接触开口，包括光源，检测器和数据处理单元。 光源适于照亮至少一部分接触开口。 检测器适于测量从接触开口的照射部分反射的光以产生反射曲线。 数据处理单元适于基于反射曲线确定接触开口的尺寸。
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3.发明授权公开(公告)号：US06650423B1
公开(公告)日：2003-11-18
申请号：US09897623
申请日：2001-07-02
IPC分类号： G01B1100
CPC分类号： G01B11/00
摘要： A test structure includes a plurality of trenches and a plurality of columns defined in the trenches. A method for determining column dimensions includes providing a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches; illuminating at least a portion of the columns with a light source; measuring light reflected from the illuminated portion of the columns to generate a reflection profile; and determining a dimension of the columns based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the columns. The detector is adapted to measure light reflected from the illuminated portion of the columns to generate a reflection profile. The data processing unit is adapted to determine a dimension of the columns based on the reflection profile.
摘要翻译： 测试结构包括多个沟槽和限定在沟槽中的多个列。 用于确定柱尺寸的方法包括提供具有测试结构的晶片，该测试结构包括限定在沟槽中的多个沟槽和多个列; 用光源照射柱的至少一部分; 测量从所述列的被照亮部分反射的光以产生反射曲线; 以及基于所述反射概况确定所述列的尺寸。 适于接收具有包括多个沟槽的测试结构的晶片的测量工具和在沟槽中限定的多个列包括光源，检测器和数据处理单元。 光源适于照亮柱的至少一部分。 检测器适于测量从列的照明部分反射的光以产生反射曲线。 数据处理单元适于基于反射曲线来确定列的尺寸。
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4.发明授权公开(公告)号：US06716646B1
公开(公告)日：2004-04-06
申请号：US09906517
申请日：2001-07-16
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： The present invention provides for a method and an apparatus for overlay measurements using optical techniques. At least one semiconductor device is processed. Metrology data from the processed semiconductor device is acquired. A scatterometry overlay analysis based upon the metrology data is performed. At least one modified manufacturing parameter is calculated based upon the scatterometry overlay analysis.
摘要翻译： 本发明提供一种使用光学技术进行覆盖测量的方法和装置。 至少一个半导体器件被处理。 获取来自处理后的半导体器件的计量数据。 执行基于测量数据的散射测绘覆盖分析。 基于散点分析叠加分析计算至少一个修改后的制造参数。
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公开(公告)号：US06458610B1
公开(公告)日：2002-10-01
申请号：US09871015
申请日：2001-05-31
IPC分类号： G01R3126
CPC分类号： H01L22/20 , G01N21/95607 , H01L2223/54453
摘要： A method and an apparatus for performing film stack fault detection. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a film stack on the semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
摘要翻译： 一种用于执行薄膜叠层故障检测的方法和装置。 至少一个半导体晶片被处理。 获得来自处理后的半导体晶片的计量数据。 访问包括与半导体晶片上的薄膜叠层相关的光学数据的参考库的数据。 将测量数据与参考库中的数据进行比较。 响应于测量数据和参考库数据的比较，执行故障检测分析。
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6.发明授权Method and apparatus for identifying misregistration in a complimentary phase shift mask process 有权用于识别互补相移掩模工艺中的对准不良的方法和装置公开(公告)号：US06774998B1
公开(公告)日：2004-08-10
申请号：US10034790
申请日：2001-12-27
IPC分类号： G01B1100
CPC分类号： G03F7/70633
摘要： A method includes providing a wafer having a first grating structure and a second grating structure formed in a photoresist layer. At least a portion of the first and second grating structures is illuminated with a light source. Light reflected from the illuminated portion of the first and second grating structures is measured to generate a reflection profile. Misregistration between the first and second grating structures is determined based on the reflection profile. A processing line includes a photolithography stepper, a metrology tool, and a controller. The photolithography stepper is adapted to process wafers in accordance with an operating recipe. The metrology tool is adapted to receive a wafer processed in the stepper. The wafer has a first grating structure and a second grating structure formed in a photoresist layer. The metrology tool includes a light source, a detector, and a data processing unit.
摘要翻译： 一种方法包括提供具有形成在光致抗蚀剂层中的第一光栅结构和第二光栅结构的晶片。 用光源照射第一和第二光栅结构的至少一部分。 测量从第一和第二光栅结构的照明部分反射的光以产生反射曲线。 基于反射曲线确定第一和第二光栅结构之间的对准。 处理线包括光刻步进机，计量工具和控制器。 光刻步进器适于根据操作配方处理晶片。 计量工具适于接收在步进器中处理的晶片。 晶片具有形成在光致抗蚀剂层中的第一光栅结构和第二光栅结构。 计量工具包括光源，检测器和数据处理单元。
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7.发明授权公开(公告)号：US06766215B1
公开(公告)日：2004-07-20
申请号：US10610942
申请日：2003-07-01
IPC分类号： G06F1900
CPC分类号： H01L22/20 , G01N21/95607 , H01L2223/54453
摘要： A method and an apparatus for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
摘要翻译： 一种在半导体制造过程中检测颈缩误差的方法和装置。 至少一个半导体晶片被处理。 获得来自处理后的半导体晶片的计量数据。 访问包括与半导体晶片上的多晶硅结构相关的光学数据的参考库的数据。 将测量数据与参考库中的数据进行比较。 响应于测量数据和参考库数据的比较，执行故障检测分析。
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8.发明授权公开(公告)号：US06657716B1
公开(公告)日：2003-12-02
申请号：US09863598
申请日：2001-05-23
IPC分类号： G01N2188
CPC分类号： H01L22/20 , G01N21/95607 , H01L2223/54453
摘要： A method and an apparatus for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
摘要翻译： 一种在半导体制造过程中检测颈缩误差的方法和装置。 至少一个半导体晶片被处理。 获得来自处理后的半导体晶片的计量数据。 访问包括与半导体晶片上的多晶硅结构相关的光学数据的参考库的数据。 将测量数据与参考库中的数据进行比较。 响应于测量数据和参考库数据的比较，执行故障检测分析。
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公开(公告)号：US06864556B1
公开(公告)日：2005-03-08
申请号：US10335445
申请日：2002-12-31
申请人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
发明人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
IPC分类号： G03F7/09 , H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/47 , H01L31/0232
CPC分类号： H01L21/32139 , G03F7/091 , H01L21/0332 , H01L21/28123 , H01L29/785
摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.
摘要翻译： 采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形 形成在可图案层中。 有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。 有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。
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公开(公告)号：US06426262B1
公开(公告)日：2002-07-30
申请号：US09644735
申请日：2000-08-23
IPC分类号： H01L218236
CPC分类号： H01L29/66492 , H01L21/26586
摘要： The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.
摘要翻译： 本发明涉及一种包括形成多个晶体管的方法，每个晶体管具有至少一个栅电极，并且在晶体管中形成晕圈注入区，同时改变光晕注入角，掩模层高度和 屏蔽层与晶体管的栅电极的横向偏移。 该方法还包括确定晶体管中的至少一些晶体管的电性能特征，其中，所述卤素注入角，掩模层高度和掩模层的横向偏移中的至少一个不同，以及将所确定的电性能特性 晶体管。
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