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11 条记录 (耗时 0.027 秒)

    On-chip decoupling capacitor and method of making same
    1.
    发明授权
    On-chip decoupling capacitor and method of making same 有权
    片上去耦电容及其制作方法

    公开(公告)号：US06737728B1

    公开(公告)日：2004-05-18

    申请号：US09687906

    申请日：2000-10-12

    申请人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    发明人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    IPC分类号： H01L27108

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53238 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

    摘要翻译： 公开了片上去耦电容器结构以及制造这种去耦电容器的方法。 在本发明的一个实施例中，电容器堆叠可以由底部电极/屏障组成; 具有高介电常数的薄介电材料; 和顶部电极/屏障。 在替代实施例中，底部电极和/或底部金属互连层具有三维结构以增加电容器的表面积。 体现本发明的说明性方法包括制造片上去耦电容器堆叠结构并电连接电容器以提供有效的电容去耦合。

    Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness
    3.
    发明授权
    Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness 有权
    形成具有表面粗糙度的底部电极层的片上去耦电容器的方法

    公开(公告)号：US07960226B2

    公开(公告)日：2011-06-14

    申请号：US11317694

    申请日：2005-12-23

    申请人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    发明人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53238 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling. In order to facilitate the removal of photoresist by an oxygen plasma process prior to exposing copper conductors during the capacitor stack etch, an Al hardmask can be used to protect the capacitor formed with Ta2O5 dielectric, or a W hardmask can be used to protect the capacitor formed with BST dielectric.

    摘要翻译： 公开了片上去耦电容器结构以及制造这种去耦电容器的方法。 片内去耦电容有助于在高浪涌电流条件下降低或防止电网上的L di / dt电压下降。 将一个或多个去耦电容器包含在靠近电力电网导体的芯片上减小了寄生电感，从而提供了相对于高频噪声的改进的去耦性能。 在本发明的一个实施例中，在金属互连层之间插入电容器堆叠结构。 这样的电容器堆叠可以由底部电极/屏障组成; 具有高介电常数的薄介电材料; 和顶部电极/屏障。 在替代实施例中，底部电极和/或底部金属互连层具有三维结构以增加电容器的表面积。 体现本发明的说明性方法包括制造片上去耦电容器堆叠结构并电连接电容器以提供有效的电容去耦合。 为了在电容器堆叠蚀刻期间在铜导体暴露之前通过氧​​等离子体工艺来促进光致抗蚀剂的去除，可以使用Al硬掩模来保护由Ta2O5电介质形成的电容器，或者可以使用W硬掩模来保护电容器 用BST电介质形成。

    Method of forming on-chip decoupling capacitor by selectively etching grain boundaries in electrode
    5.
    发明授权
    Method of forming on-chip decoupling capacitor by selectively etching grain boundaries in electrode 失效
    通过选择性蚀刻电极中的晶界来形成片上去耦电容的方法

    公开(公告)号：US07033882B2

    公开(公告)日：2006-04-25

    申请号：US10760080

    申请日：2004-01-15

    申请人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    发明人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/8242

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53238 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling. In order to facilitate the removal of photoresist by an oxygen plasma process prior to exposing copper conductors during the capacitor stack etch, an Al hardmask can be used to protect the capacitor formed with Ta2O5 dielectric, or a W hardmask can be used to protect the capacitor formed with BST dielectric.

    摘要翻译： 公开了片上去耦电容器结构以及制造这种去耦电容器的方法。 片内去耦电容有助于在高浪涌电流条件下降低或防止电网上的L di / dt电压下降。 将一个或多个去耦电容器包含在靠近电力电网导体的芯片上减小了寄生电感，从而提供了相对于高频噪声的改进的去耦性能。 在本发明的一个实施例中，在金属互连层之间插入电容器堆叠结构。 这样的电容器堆叠可以由底部电极/屏障组成; 具有高介电常数的薄介电材料; 和顶部电极/屏障。 在替代实施例中，底部电极和/或底部金属互连层具有三维结构以增加电容器的表面积。 体现本发明的说明性方法包括制造片上去耦电容器堆叠结构并电连接电容器以提供有效的电容去耦合。 为了在电容器堆叠蚀刻期间在铜导体暴露之前通过氧​​等离子体工艺促进光致抗蚀剂的去除，可以使用Al硬掩模来保护由Ta 2 O 5形成的电容器 电介质或W硬掩模可用于保护由BST电介质形成的电容器。

    Layer transfer technique
    6.
    发明申请
    Layer transfer technique 审中-公开
    层传输技术

    公开(公告)号：US20060286771A1

    公开(公告)日：2006-12-21

    申请号：US11509147

    申请日：2006-08-23

    申请人： Mohamad Shaheen ,  Ruitao Zhang ,  Ryan Lei

    发明人： Mohamad Shaheen ,  Ruitao Zhang ,  Ryan Lei

    IPC分类号： H01L21/30

    CPC分类号： H01L21/76254

    摘要： A layer transfer technique in which a portion of a donor wafer is doped with positively charged hydrogen ions and positively charged helium ions before it is bonded to a portion of a handle wafer. Furthermore, the bonded wafers are annealed at one of two annealing temperatures, which determines whether the wafers are separated using a thermal cleave or a mechanical cleave process.

    摘要翻译： 施主晶片的一部分在被接合到处理晶片的一部分之前掺杂有带正电荷的氢离子和带正电荷的氦离子的层转移技术。 此外，接合的晶片在两个退火温度中的一个退火温度下进行退火，这确定晶片是否使用热劈裂或机械劈裂工艺分离。