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1.发明授权Row decoder circuit for an electronic memory device, particularly for low voltage applications 有权用于电子存储器件的行解码器电路，特别是用于低电压应用
公开(公告)号：US6069837A
公开(公告)日：2000-05-30
申请号：US222022
申请日：1998-12-29
IPC分类号： G11C16/06 , G11C8/08 , G11C11/408 , G11C8/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, is described. The row decoding circuit is adapted to boost, through at least one boost capacitor, a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference and a second ground potential reference, and comprises a hierarchic structure of cascade connected inverters and a circuit means of progressively raising the read voltage level dynamically. First means are provided for raising the read voltage level to a value equal to the supply voltage plus a threshold voltage, and second means are provided for raising the read voltage level to a value equal to the supply voltage plus twice said threshold voltage.
摘要翻译： 描述了用于电子存储单元装置的行解码电路，特别是在低电压应用中。 行解码电路适于通过至少一个升压电容器升高要施加到包含要读取的存储器单元的存储器列的读取电压。 电路在第一电源参考电压和第二接地电位基准之间供电，并且包括级联连接的反相器的分级结构和逐渐提高读取电压电平的电路装置。 提供了用于将读取电压电平升高到等于电源电压加上阈值电压的值的第一装置，并且提供第二装置，用于将读取电压电平升高到等于电源电压加上两倍阈值电压的值。
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公开(公告)号：US06169423A
公开(公告)日：2001-01-02
申请号：US09186496
申请日：1998-11-04
IPC分类号： H03K522
CPC分类号： G11C8/18
摘要： The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.
摘要翻译： 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便还产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。
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公开(公告)号：US6144589A
公开(公告)日：2000-11-07
申请号：US186758
申请日：1998-11-05
摘要： A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable for generating the third voltage level and selectively coupleable to the output line.
摘要翻译： 由第一电压电平和第二电压电平提供的升压电路，并具有能够获得第三电压电平的输出线，所述电路具有用于产生第三电压电平的至少两个不同的电路，所述至少两个电路可选择地激活 用于产生第三电压电平并选择性地耦合到输出线。
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公开(公告)号：US06396168B2
公开(公告)日：2002-05-28
申请号：US09782173
申请日：2001-02-12
IPC分类号： H03K19096
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1778 , Y10T307/505
摘要： A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.
摘要翻译： 可编程逻辑阵列（PLA）包括至少一个AND平面，其包括以行和列排列的晶体管阵列。 属于同一列的晶体管可以彼此串联连接。 串联连接的晶体管的两个端部导电端子可以分别耦合到电源电压轨和参考。 阵列的第一行和最后一行的晶体管可以使它们的控制端耦合到各自相对的使能/禁止电位。 除了第一行和最后一行，第一，第二和第三控制行都与数组的每一行相关联。 除了第一行和最后一行之外，每行的每个晶体管可以将其控制端连接到与其行相关联的三条控制线之一。 PLA可以替代地包括至少一个OR平面。
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5.发明授权Electronic counter for a non-volatile memory device integrated on a semiconductor 有权用于集成在半导体上的非易失性存储器件的电子计数器公开(公告)号：US06208705B1
公开(公告)日：2001-03-27
申请号：US09262500
申请日：1999-03-04
IPC分类号： G06M300
摘要： An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.
摘要翻译： 一种用于半导体集成非易失性存储器件的电子计数器，包括与其输出端连接至至少一个存储元件的单个计数单元。该计数单元包括半加法器类型的加法块和主/从器件的主器件 其中所述存储元件是从属部分的触发器。 有利地，主机部分具有连接到平行布置的数个n个从属寄存器的输入侧的输出。
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6.发明授权Method and system for managing address bits during buffered program operations in a memory device 有权用于在存储器件中缓存的程序操作期间管理地址位的方法和系统公开(公告)号：US07404049B2
公开(公告)日：2008-07-22
申请号：US11123682
申请日：2005-05-06
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G11C16/10 , G11C2216/14
摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.
摘要翻译： 描述用于管理用于多个单词的缓冲程序操作的方法和系统。 一方面，该方法和系统包括提供包括多个位置的多个位置和至少一个位置的内部缓冲器。 每个词都存储在多个位置的位置。 这些单词与位置的内部地址位相关联。 至少一个内部地址位是与所有字对应的至少一个组地址位。 内部地址位的剩余部分与至少一个字相关联。 所述至少一个位位置存储所述字的至少一个组地址位。 因此，在一个方面，该方法和系统包括将每个单词存储在缓冲器位置之一中。 该方法和系统还包括将至少一个组地址位与每个字的缓冲器位置相关联。
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公开(公告)号：US07826291B2
公开(公告)日：2010-11-02
申请号：US12174307
申请日：2008-07-16
IPC分类号： G11C7/00
摘要： A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.
摘要翻译： 用于存储读出放大器的预充电和评估电路包括具有耦合到电源电位的源极的第一预充电相晶体管，耦合到预充电控制线的栅极和漏极。 第二预充电相晶体管具有耦合到第一预充电相晶体管的漏极的漏极，源极和通过反馈电路耦合到源极的栅极。 第一读取相晶体管具有耦合到电源电位的源极，以及耦合到比较器的栅极和漏极。 第二读取相位晶体管具有耦合到第一读取相位晶体管的漏极的漏极，耦合到第二预充电相位晶体管的源极的栅极，以及耦合到第二读取相位晶体管的源极的栅极， 一个反馈电路。 列解码器耦合到第二预充电相位和第二读相晶体管的源极。
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公开(公告)号：US20100014370A1
公开(公告)日：2010-01-21
申请号：US12174307
申请日：2008-07-16
IPC分类号： G11C7/00
摘要： A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.
摘要翻译： 用于存储读出放大器的预充电和评估电路包括具有耦合到电源电位的源极的第一预充电相晶体管，耦合到预充电控制线的栅极和漏极。 第二预充电相晶体管具有耦合到第一预充电相晶体管的漏极的漏极，源极和通过反馈电路耦合到源极的栅极。 第一读取相晶体管具有耦合到电源电位的源极，以及耦合到比较器的栅极和漏极。 第二读取相位晶体管具有耦合到第一读取相位晶体管的漏极的漏极，耦合到第二预充电相位晶体管的源极的栅极，以及耦合到第二读取相位晶体管的源极的栅极， 一个反馈电路。 列解码器耦合到第二预充电相位和第二读相晶体管的源极。
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公开(公告)号：US07573748B2
公开(公告)日：2009-08-11
申请号：US11652828
申请日：2007-01-12
IPC分类号： G11C16/06
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译： 感测电路。 在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置以及耦合到补偿装置的补偿电路。 补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。 补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。 根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。
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10.发明申请Method and system for managing address bits during buffered program operations in a memory device 有权用于在存储器件中缓存的程序操作期间管理地址位的方法和系统公开(公告)号：US20060085622A1
公开(公告)日：2006-04-20
申请号：US11123682
申请日：2005-05-06
申请人： Simone Bartoli , Stefano Surico , Davide Manfre , Donato Ferrario
发明人： Simone Bartoli , Stefano Surico , Davide Manfre , Donato Ferrario
IPC分类号： G06F12/10
CPC分类号： G06F12/04 , G11C16/10 , G11C2216/14
摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.
摘要翻译： 描述用于管理用于多个单词的缓冲程序操作的方法和系统。 一方面，该方法和系统包括提供包括多个位置的多个位置和至少一个位置的内部缓冲器。 每个词都存储在多个位置的位置。 这些单词与位置的内部地址位相关联。 至少一个内部地址位是与所有字对应的至少一个组地址位。 内部地址位的剩余部分与至少一个字相关联。 所述至少一个位位置存储所述字的至少一个组地址位。 因此，在一个方面，该方法和系统包括将每个单词存储在缓冲器位置之一中。 该方法和系统还包括将至少一个组地址位与每个字的缓冲器位置相关联。
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