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公开(公告)号：US06351413B1
公开(公告)日：2002-02-26
申请号：US09552945
申请日：2000-04-20
IPC分类号： G11C1604
摘要： The memory array comprises a plurality of cells, grouped together in sectors and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines are connected to at least two word lines in each sector, through local row decoders; global bit lines are connected to at least two local bit lines in each sector, through local column decoders. The global column decoder is arranged in the center of the memory array, and separates from each other an upper half and a lower half of the memory array. Sense amplifiers are also arranged in the middle of the array, thus saving space. This architecture also provides lesser stress of the cells, better reliability, and better production performance. In addition, each sector is completely disconnected from the remaining sectors, and only the faulty row or column of a single sector should be doubled.
摘要翻译： 存储器阵列包括多个单元，分组在扇区中并以扇区行和列排列，并且具有分级行解码和分层列解码。 全局字线通过局部行解码器连接到每个扇区中的至少两个字线; 全局位线通过本地列解码器连接到每个扇区中的至少两个局部位线。 全局列解码器被布置在存储器阵列的中心，并且彼此分离存储器阵列的上半部和下半部。 感应放大器也布置在阵列的中间，从而节省空间。 该架构还提供更小的电池应力，更好的可靠性和更好的生产性能。 此外，每个扇区与其余扇区完全断开连接，只有单个扇区的故障行或列应该加倍。
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2.发明授权Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory 有权方法和相关电路，用于调整同步信号ATD的持续时间，用于定时访问非易失性存储器公开(公告)号：US06237104B1
公开(公告)日：2001-05-22
申请号：US09222070
申请日：1998-12-29
IPC分类号： G06F1200
摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
摘要翻译： 讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。 当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。 该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。 逻辑和用于启动读取阶段。
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3.发明授权Method and circuit for reading low-supply-voltage nonvolatile memory cells 失效读取低电压 - 非易失性存储单元的方法和电路
公开(公告)号：US6128225A
公开(公告)日：2000-10-03
申请号：US879017
申请日：1997-06-18
CPC分类号： G11C16/28
摘要： The read circuit has an array branch connected to an array cell, and a reference branch connected to a reference cell; the array branch presents an array load transistor interposed between a supply line and the array cell, and the reference branch presents a reference load transistor interposed between the supply line and the reference cell; and the array and reference load transistors form a current mirror wherein the array load transistor is diode-connected and presents a first predetermined channel width/length ratio, and the reference load transistor presents a second predetermined channel width/length ratio N times greater than the first ratio, so that the current flowing in the array cell is supplied, amplified, to the reference branch.
摘要翻译： 读取电路具有连接到阵列单元的阵列分支和连接到参考单元的参考分支; 阵列分支呈现插入在电源线和阵列单元之间的阵列负载晶体管，参考支路呈现插在电源线和参考单元之间的基准负载晶体管; 并且阵列和参考负载晶体管形成电流镜，其中阵列负载晶体管是二极管连接的并且呈现第一预定沟道宽度/长度比，并且参考负载晶体管呈现第二预定沟道宽/长比N 使得流过阵列单元的电流被提供，放大到参考分支。
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公开(公告)号：US5903498A
公开(公告)日：1999-05-11
申请号：US877927
申请日：1997-06-18
CPC分类号： G11C16/08
摘要： The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.
摘要翻译： 存储器件具有多个本地升压电路，每个局部升压电路各自连接到存储器阵列的扇区，并且每个具有控制电路，至少相应的升压电容器和相应的驱动电路。 每个驱动电路仅在读取模式下被启用，在接收到地址转换检测信号和扇区使能信号时，用于读取形成相应扇区的一部分的存储器单元。 升压电压仅提供给行解码器的最终反相器。 钳位二极管限制升压电压，以防止连接到非寻址字线的最终逆变器的PMOS晶体管的不期望的直接偏置。 因此，过电压仅在必要时在当地提供。
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公开(公告)号：US6018255A
公开(公告)日：2000-01-25
申请号：US862563
申请日：1997-05-23
IPC分类号： G11C8/10 , G11C16/12 , H03K19/082
摘要： The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.
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6.发明授权Single-cell reference signal generating circuit for reading nonvolatile memory 失效用于读取非易失性存储器的单单元参考信号发生电路
公开(公告)号：US5946238A
公开(公告)日：1999-08-31
申请号：US877066
申请日：1997-06-17
CPC分类号： G11C16/28
摘要： A nonvolatile memory having a memory array including a plurality of data cells and a read circuit. The read circuit includes a plurality of sense amplifiers, each connected to a respective array branch to be connected to the data cells. The nonvolatile memory also includes a reference generating circuit including a single reference cell arranged outside the memory array and generates a reference signal. The reference generating circuit includes a plurality of reference branches, each connected to a respective sense amplifier, and circuits interposed between the reference cell and the reference branches to supply the reference branches with a signal based on the reference signal.
摘要翻译： 一种具有包括多个数据单元和读取电路的存储器阵列的非易失性存储器。 读取电路包括多个读出放大器，每个读出放大器连接到要连接到数据单元的相应的阵列分支。 非易失性存储器还包括参考产生电路，其包括布置在存储器阵列外部的单个参考单元并产生参考信号。 参考产生电路包括多个参考分支，每个参考分支连接到相应的读出放大器，以及插入参考单元和参考分支之间的电路，以基于参考信号为参考分支提供信号。
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公开(公告)号：US6094073A
公开(公告)日：2000-07-25
申请号：US432642
申请日：1999-11-02
IPC分类号： G11C8/10 , G11C16/12 , H03K19/082
摘要： The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.
摘要翻译： 行解码器包括提供有行地址并产生预解码信号的预解码级; 以及最终解码阶段，其基于预解码信号驱动阵列中的各行。 预解码阶段包括多个预解码电路，其呈现两个并行信号路径：在读取模式中使用的低电压路径，以及在编程模式中使用的高压路径。 CMOS开关将两路径分开，通过编程模式下的电压转换器由高电压驱动，并且在预解码级别形成，不涉及集成问题。
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8.发明授权Voltage regulator or non-volatile memories implemented with low-voltage transistors 有权用低压晶体管实现的稳压器或非易失性存储器公开(公告)号：US07777466B2
公开(公告)日：2010-08-17
申请号：US11844470
申请日：2007-08-24
IPC分类号： G05F1/40
摘要： A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.
摘要翻译： 提供集成在半导体材料芯片中的电压调节器。 所述调节器具有用于接收第一电压的第一输入端子和用于提供从所述第一电压获得的调节电压的输出端子，所述调节器包括：用于接收比较电压的差分放大器和作为所述第一电压的函数的反馈信号 电压，并且为了根据比较电压和反馈信号之间的比较来证明调节信号，差分放大器具有与用于接收参考电压的参考端子耦合的第一电源端子和第二电源端子，调节晶体管具有 用于接收所述调节信号的控制端子，以及通过所述参考端子和所述调节器的所述第一输入端子之间的负载装置耦合的导通第一端子和导通第二端子，所述调节晶体管的所述第二端子与所述输出端子 的调节器，其中第二电源 差分放大器的nal与调节器的第二输入端耦合，用于接收低于绝对值中的第一电压的第二电压，并且其中调节器还包括一组辅助晶体管，串联连接在第二端 调节器的调节晶体管和输出端子，以及用于根据调节电压控制辅助晶体管的控制装置。
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公开(公告)号：US07027317B2
公开(公告)日：2006-04-11
申请号：US10720013
申请日：2003-11-20
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
CPC分类号： G11C11/005
摘要： A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.
摘要翻译： 半导体存储器包括多个存储器单元，例如布置在多个行中的闪存单元，以及多个存储单元存取信号线，每个存储单元接入信号线与至少一个相应行的存储单元相关联，用于访问存储器 存储单元的至少一个相应行的单元; 每个信号线具有与其固有相关的电容。 提供了多个易失性存储单元，每个易失性存储单元具有电容存储元件。 每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。 特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。
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公开(公告)号：US06327184B1
公开(公告)日：2001-12-04
申请号：US09621019
申请日：2000-07-21
申请人： Rino Micheloni , Giovanni Campardo , Luca Crippa
发明人： Rino Micheloni , Giovanni Campardo , Luca Crippa
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output array node of the array branch and to an output reference node of the reference branch to supply on the output array node and the output reference node the respective electric potentials correlated to the currents flowing in the array memory cell and, respectively, in the reference memory cell; and a comparator connected at input to the output array node and output reference node and supplying as output a signal indicative of the contents stored in the array memory cell; and an array decoupling stage arranged between the input array node and the output array node to decouple the electric potentials of the input and output array nodes from one another.
摘要翻译： 读取电路包括具有通过阵列位线连接到阵列单元的输入阵列节点的阵列分支; 参考分支，其具有通过参考位线连接到参考单元的输入参考节点; 连接到阵列分支的输出阵列节点和参考分支的输出参考节点的电流 - 电压转换器，以在输出阵列节点和输出参考节点上提供与在 阵列存储单元，分别在参考存储单元中; 以及比较器，其输入端连接到所述输出阵列节点和输出参考节点，并且作为输出提供指示存储在所述阵列存储单元中的内容的信号; 以及布置在输入阵列节点和输出阵列节点之间的阵列解耦级，以将输入和输出阵列节点的电位彼此去耦。
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