公开(公告)号：US07190077B2

公开(公告)日：2007-03-13

申请号：US10519860

申请日：2003-06-12

申请人： Robert Bauer ,  Werner Ertle ,  Till Frohnmüller ,  Bernd Goller ,  Reinhard Greiderer ,  Oliver Nagler ,  Olaf Schmeckebier ,  Wolfgang Stadler

发明人： Robert Bauer ,  Werner Ertle ,  Till Frohnmüller ,  Bernd Goller ,  Reinhard Greiderer ,  Oliver Nagler ,  Olaf Schmeckebier ,  Wolfgang Stadler

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00

摘要： An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least—part of the semiconductor element.Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.

摘要翻译： 集成半导体结构具有衬底，位于衬底上的半导体元件，焊盘金属，位于焊盘金属和​​衬底之间的金属层以及将金属层彼此分离的绝缘层。 焊盘金属在半导体元件的至少一部分上延伸。 在焊盘金属的表面下方，至少顶部的两个金属层包括两个或更多相邻的互连。

公开(公告)号：US20050242374A1

公开(公告)日：2005-11-03

申请号：US10519860

申请日：2003-06-12

申请人： Robert Bauer ,  Werner Ertle ,  Till Frohnmuller ,  Bernd Goller ,  Reinhard Greiderer ,  Oliver Nagler ,  Olaf Schmeckebier ,  Wolfgang Stadler

发明人： Robert Bauer ,  Werner Ertle ,  Till Frohnmuller ,  Bernd Goller ,  Reinhard Greiderer ,  Oliver Nagler ,  Olaf Schmeckebier ,  Wolfgang Stadler

IPC分类号： H01L23/485 ,  H01L31/0336

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00

摘要： An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least -part of the semiconductor element. Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.

摘要翻译： 集成半导体结构具有衬底，位于衬底上的半导体元件，焊盘金属，位于焊盘金属和​​衬底之间的金属层以及将金属层彼此分离的绝缘层。 焊盘金属在半导体元件的至少一部分上延伸。 在焊盘金属的表面下方，至少顶部的两个金属层包括两个或更多相邻的互连。

公开(公告)号：US20050285199A1

公开(公告)日：2005-12-29

申请号：US11137691

申请日：2005-05-25

申请人： Wolfgang Stadler ,  Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Manfred Hermann ,  Giuseppe Miccoli

发明人： Wolfgang Stadler ,  Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Manfred Hermann ,  Giuseppe Miccoli

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/50 ,  H01L23/62

CPC分类号： H01L24/05 ,  H01L23/562 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/30105 ,  H01L2924/00014

摘要： A semiconductor circuit containing a pad for electrical bonding of the semiconductor circuit and a metal arrangement disposed beneath the pad. The metal arrangement is in a metal layer of the semiconductor circuit located closest to the pad and is electrically insulated from the pad and from a strip conductor located beneath the metal arrangement. More than one metal layer can contain a metal arrangement. Each metal arrangement is a full-area plate that overlaps all edges of the pad or has a regular structure of small square plates. If adjacent metal arrangements are constructed from small plates, the plates in one metal arrangement overlap to cover gaps in the other metal arrangement.

摘要翻译： 一种半导体电路，包括用于半导体电路的电接合的焊盘和设置在焊盘下方的金属布置。 金属布置在最靠近焊盘的半导体电路的金属层中，并且与焊盘和位于金属布置下方的带状导体电绝缘。 多于一个金属层可以包含金属布置。 每个金属布置是与面板的所有边缘重叠或具有小方块的规则结构的全区域板。 如果相邻的金属布置由小板构成，则一个金属布置中的板重叠以覆盖另一金属布置中的间隙。

公开(公告)号：US20110294238A1

公开(公告)日：2011-12-01

申请号：US13192974

申请日：2011-07-28

申请人： Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Bernd Kothe

发明人： Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Bernd Kothe

IPC分类号： H01L21/66

CPC分类号： H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4943 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

摘要翻译： 本发明涉及图案化半导体芯片上的接触区域和测试区域的布置。 接触区域和测试区域通过传导网彼此电连接。 而接触区域布置在没有集成电路的部件的第一区域中，测试区域位于半导体芯片的顶侧的第二区域中，该区域具有集成电路的部件。

公开(公告)号：US08044394B2

公开(公告)日：2011-10-25

申请号：US10522502

申请日：2003-07-29

申请人： Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Bernd Kothe

发明人： Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Bernd Kothe

IPC分类号： H01L23/58

CPC分类号： H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4943 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

摘要翻译： 本发明涉及图案化半导体芯片上的接触区域和测试区域的布置。 接触区域和测试区域通过传导网彼此电连接。 而接触区域布置在没有集成电路的部件的第一区域中，测试区域位于半导体芯片的顶侧的第二区域中，该区域具有集成电路的部件。

公开(公告)号：US20060097386A1

公开(公告)日：2006-05-11

申请号：US10522502

申请日：2003-07-29

申请人： Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Bernd Kothe

发明人： Werner Ertle ,  Bernd Goller ,  Michael Horn ,  Bernd Kothe

IPC分类号： H01L23/34

CPC分类号： H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4943 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

摘要翻译： 本发明涉及图案化半导体芯片上的接触区域和测试区域的布置。 接触区域和测试区域通过传导网彼此电连接。 而接触区域布置在没有集成电路的部件的第一区域中，测试区域位于半导体芯片的顶侧的第二区域中，该区域具有集成电路的部件。

公开(公告)号：US08466009B2

公开(公告)日：2013-06-18

申请号：US12779367

申请日：2010-05-13

申请人： Bernd Goller ,  Markus Dinkel ,  Wae Chet Yong ,  Teck Sim Lee ,  Boon Kian Lim

发明人： Bernd Goller ,  Markus Dinkel ,  Wae Chet Yong ,  Teck Sim Lee ,  Boon Kian Lim

IPC分类号： H01L23/28 ,  H01L23/495

CPC分类号： H01L23/49548 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer.

摘要翻译： 一种半导体封装的制造方法。 在一个实施例中，该方法包括在引线框架的第一主表面的一部分周围形成模腔，包括在第一主表面和第二主表面之间延伸穿过引线框架的模具锁定开口。 插入间隔件以填充模具锁定开口的至少一部分。 模腔填充有包封材料，包括填充未被间隔件占据的模具锁定开口的一部分。

公开(公告)号：US07732937B2

公开(公告)日：2010-06-08

申请号：US12041757

申请日：2008-03-04

申请人： Bernd Goller ,  Markus Dinkel ,  Wae Chet Yong ,  Teck Sim Lee ,  Boon Kian Lim

发明人： Bernd Goller ,  Markus Dinkel ,  Wae Chet Yong ,  Teck Sim Lee ,  Boon Kian Lim

IPC分类号： H01L23/495 ,  H01L23/28 ,  H01L29/40

CPC分类号： H01L23/49548 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.

摘要翻译： 一种半导体封装，包括具有第一和第二主表面的引线框和在第一和第二主表面之间延伸的模具锁定开口。 半导体封装包括耦合到第一主表面的半导体管芯和围绕半导体芯片形成的封装材料和引线框架的第一主表面的一部分，并且填充模具锁定开口的除了一部分之外的所有部分， 所述模具锁定开口形成从所述第二主表面延伸到所述第一主表面的通气口，所述排气口提供用于空气从所述第二主表面与所述第二主表面所要附接到的表面之间逸出的通路。

公开(公告)号：US20090224382A1

公开(公告)日：2009-09-10

申请号：US12041757

申请日：2008-03-04

申请人： Bernd Goller ,  Markus Dinkel ,  Wae Chet Yong ,  Teck Sim Lee ,  Boon Kian Lim

发明人： Bernd Goller ,  Markus Dinkel ,  Wae Chet Yong ,  Teck Sim Lee ,  Boon Kian Lim

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49548 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.

摘要翻译： 一种半导体封装，包括具有第一和第二主表面的引线框和在第一和第二主表面之间延伸的模具锁定开口。 半导体封装包括耦合到第一主表面的半导体管芯和围绕半导体芯片形成的封装材料和引线框架的第一主表面的一部分，并且填充模具锁定开口的除了一部分之外的所有部分， 所述模具锁定开口形成从所述第二主表面延伸到所述第一主表面的通气口，所述排气口提供用于空气从所述第二主表面与所述第二主表面所要附接到的表面之间逸出的通路。

公开(公告)号：US20090212404A1

公开(公告)日：2009-08-27

申请号：US12038458

申请日：2008-02-27

申请人： Lee Teck Sim ,  Yong Wae Chet ,  Bernd Goller ,  Lim Boon Kian

发明人： Lee Teck Sim ,  Yong Wae Chet ,  Bernd Goller ,  Lim Boon Kian

IPC分类号： H01L23/495 ,  H05K7/18 ,  H01L21/60

CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe for supporting a semiconductor chip, the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge, and an opening spaced from the at least one perimeter edge and extending through the thickness of the die pad between the first and second major surfaces. A vent extends from the at least one perimeter edge to the opening so that the opening is in communication with the at least one perimeter edge.

摘要翻译： 一种用于支撑半导体芯片的引线框，所述引线框架包括具有第一主表面和限定厚度并具有至少一个周边边缘的相对的第二主表面的管芯焊盘，以及与所述至少一个周边边缘间隔开并延伸穿过 第一和第二主表面之间的管芯焊盘的厚度。 排气口从所述至少一个周边边缘延伸到所述开口，使得所述开口与所述至少一个周边边缘连通。