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    Method for fabricating a novel metallized oxide structure
    1.
    发明授权
    Method for fabricating a novel metallized oxide structure 失效
    制造新型金属化氧化物结构的方法

    公开(公告)号：US06271076B1

    公开(公告)日：2001-08-07

    申请号：US09289226

    申请日：1999-04-09

    申请人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw ,  Joseph M. Viggiano

    发明人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw ,  Joseph M. Viggiano

    IPC分类号： H01L218242

    CPC分类号： H01G4/008

    摘要： A structure and method for providing an interface with an oxide surface which exhibits both high adhesion and preferred electrical properties. The method involves providing a partial layer of a first material, chosen for its electrical properties, whereby the partial layer has openings through which areas of the oxide surface are exposed. Provision of the partial layer is followed by deposition of a continuous layer of a second material, selected for its preferred physical interface properties, i.e., adhesion. The continuous layer of the second material is deposited over the partial layer including the exposed areas of the oxide surface. The second material will adhere to the exposed areas of oxide, while the first material will provide a discrete interface with the oxide. An embodiment includes a capacitor structure having one or two electrodes abutting a high dielectric thin film, whereby the electrodes comprise first partial layers of metal having favorable electrical properties and second continuous layers adjacent the first partial layers, with the second layer material having been chosen for its physical properties, and wherein the second material adheres to exposed areas of the thin film through openings in the partial metal layer.

    摘要翻译： 用于提供具有高粘合性和优选电性能的氧化物表面的界面的结构和方法。 该方法包括提供根据其电性质选择的第一材料的部分层，由此部分层具有暴露氧化物表面的区域的开口。 随后提供部分层，随后沉积由其优选的物理界面性质（即粘附性）选择的第二材料的连续层。 第二材料的连续层沉积在包括氧化物表面的暴露区域的部分层上。 第二种材料将附着在暴露的氧化物区域，而第一种材料将提供与氧化物的离散界面。 一个实施例包括具有一个或两个电极邻接高电介质薄膜的电容器结构，由此电极包括具有良好电性能的第一部分金属层和与第一部分层相邻的第二连续层，其中第二层材料被选择用于 其物理性质，并且其中第二材料通过部分金属层中的开口粘附在薄膜的暴露区域上。

    Lead silicate based capacitor structures
    2.
    发明授权
    Lead silicate based capacitor structures 失效
    硅酸铅基电容器结构

    公开(公告)号：US6088216A

    公开(公告)日：2000-07-11

    申请号：US431349

    申请日：1995-04-28

    申请人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw

    发明人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01G4/10

    CPC分类号： H01L28/55 ,  H01G4/10 ,  H01G4/129 ,  H01L21/31691

    摘要： A capacitor and method of making is described incorporating a semiconductor substrate, a bottom electrode formed on or in the substrate, a dielectric layer of barium or lead silicate, and a top electrode. A sandwich dielectric of a barium or lead silicate and a high dielectric constant material such as barium or lead titanate may form the dielectric. The silicate layer may be formed by evaporating and diffusing, ion implanting, or electroplating and diffusing barium or lead. The high epsilon dielectric constant material may be formed by sol gel deposition, metal organic chemical vapor deposition or sputtering. The invention overcomes the problem of a bottom electrode and dielectric layer which chemically interact to form a silicon oxide layer in series or below the desired dielectric layer.

    摘要翻译： 描述了一种电容器和制造方法，其包括半导体衬底，形成在衬底上或衬底中的底部电极，钡或硅酸铅的电介质层和顶部电极。 钡或硅酸铅和高介电常数材料如钡或钛酸铅的三明治电介质可形成电介质。 硅酸盐层可以通过蒸发和扩散，离子注入或电镀和扩散钡或铅而形成。 高ε介电常数材料可以通过溶胶凝胶沉积，金属有机化学气相沉积或溅射形成。 本发明克服了底部电极和电介质层的问题，化学相互作用以形成串联或低于所需电介质层的氧化硅层。

    Metallized oxide structure and fabrication
    3.
    发明授权
    Metallized oxide structure and fabrication 失效
    金属氧化物结构和制造

    公开(公告)号：US5926360A

    公开(公告)日：1999-07-20

    申请号：US807186

    申请日：1997-02-27

    申请人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw ,  Joseph M. Viggiano

    发明人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw ,  Joseph M. Viggiano

    IPC分类号： H01G4/005 ,  H01G4/008 ,  H01G4/06 ,  H01L21/8242

    CPC分类号： H01G4/008

    摘要： A structure for providing an interface with an oxide surface which exhibits both high adhesion and preferred electrical properties. An embodiment includes a capacitor structure having one or two electrodes abutting a high dielectric thin film, whereby the electrodes comprise first partial layers of metal having favorable electrical properties and second continuous layers adjacent the first partial layers, with the second layer material having been chosen for its physical properties, and wherein the second material adheres to exposed areas of the thin film through openings in the partial metal layer.

    摘要翻译： 用于提供具有高粘合性和优选电性能的氧化物表面的界面的结构。 一个实施例包括具有一个或两个电极邻接高电介质薄膜的电容器结构，由此电极包括具有良好电性能的第一部分金属层和与第一部分层相邻的第二连续层，其中第二层材料被选择用于 其物理性质，并且其中第二材料通过部分金属层中的开口粘附在薄膜的暴露区域上。

    Amorphous dielectric capacitors on silicon
    4.
    发明授权
    Amorphous dielectric capacitors on silicon 失效
    硅上无定形介质电容器

    公开(公告)号：US06255122B1

    公开(公告)日：2001-07-03

    申请号：US09300185

    申请日：1999-04-27

    申请人： Peter Richard Duncombe ,  Robert Benjamin Laibowitz ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

    发明人： Peter Richard Duncombe ,  Robert Benjamin Laibowitz ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

    IPC分类号： H01L2100

    CPC分类号： H01L28/55

    摘要： High-capacity capacitors and gate insulators exhibiting moderately high dielectric constants with surprisingly low leakage using amorphous or low temperature films of perovskite type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, a niobate, aluminate or tantalate system material such as lead magnesium niobate, lithium niobate lithium tantalate, potassium niobate and potassium tantalum niobate, a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate, and Bi-layered perovskite system material such as strontium bismuth tantalate, bismuth titanate deposited directly on a silicon surface at temperatures about 450° C. or less.

    摘要翻译： 具有中等高介电常数的大容量电容器和栅极绝缘体，具有惊人的低泄漏性，使用包括钛酸钡系钛酸钡，钛酸锶钡，钛酸钡锶（BST），钛酸铅，铅的钛酸盐体系材料的钙钛矿型氧化物的非晶或低温膜 钛酸镧锆钛酸铅，钛酸镧钛酸镧，铌酸盐，铝酸盐或钽酸盐体系材料，如铌酸铅镁，铌酸锂锂钽酸锂，铌酸钾和铌酸钾钾，钨 - 青铜系材料如铌酸锶钡， 铅铌酸钡，铌酸钡钡和Bi-层状钙钛矿系材料如钽酸锶铋钛酸铋直接沉积在硅表面上，温度约450℃或更低。

    Lead silicate based capacitor structures
    5.
    发明授权
    Lead silicate based capacitor structures 失效
    硅酸铅基电容器结构

    公开(公告)号：US06211543B1

    公开(公告)日：2001-04-03

    申请号：US09543637

    申请日：2000-04-06

    申请人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw

    发明人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw

    IPC分类号： H01L2976

    CPC分类号： H01L28/55 ,  H01G4/10 ,  H01G4/129 ,  H01L21/31691

    摘要： A capacitor and method of making is described incorporating a semiconductor substrate, a bottom electrode formed on or in the substrate, a dielectric layer of barium or lead silicate, and a top electrode. A sandwich dielectric of a barium or lead silicate and a high dielectric constant material such as barium or lead titanate may form the dielectric. The silicate layer may be formed by evaporating and diffusing, ion implanting, or electroplating and diffusing barium or lead. The high epsilon dielectric constant material may be formed by sol gel deposition, metal organic chemical vapor deposition or sputtering. The invention overcomes the problem of a bottom electrode and dielectric layer which chemically interact to form a silicon oxide layer in series or below the desired dielectric layer.

    摘要翻译： 描述了一种电容器和制造方法，其包括半导体衬底，形成在衬底上或衬底中的底部电极，钡或硅酸铅的电介质层和顶部电极。 钡或硅酸铅和高介电常数材料如钡或钛酸铅的三明治电介质可形成电介质。 硅酸盐层可以通过蒸发和扩散，离子注入或电镀和扩散钡或铅而形成。 高ε介电常数材料可以通过溶胶凝胶沉积，金属有机化学气相沉积或溅射形成。 本发明克服了底部电极和电介质层的问题，化学相互作用以形成串联或低于所需电介质层的氧化硅层。

    Lead silicate based capacitor structures
    6.
    发明授权
    Lead silicate based capacitor structures 失效
    硅酸铅基电容器结构

    公开(公告)号：US6090659A

    公开(公告)日：2000-07-18

    申请号：US314409

    申请日：1999-05-19

    申请人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw

    发明人： Robert Benjamin Laibowitz ,  Thomas McCarroll Shaw

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L28/55 ,  H01G4/10 ,  H01G4/129 ,  H01L21/31691

    摘要： A capacitor and method of making is described incorporating a semiconductor substrate, a bottom electrode formed on or in the substrate, a dielectric layer of barium or lead silicate, and a top electrode. A sandwich dielectric of a barium or lead silicate and a high dielectric constant material such as barium or lead titanate may comprise the dielectric. The silicate layer may be formed by evaporating and diffusing, ion implanting, or electroplating and diffusing barium or lead. The high epsilon dielectric constant material may be formed by sol gel deposition, metal organic chemical vapor deposition or sputtering. The invention overcomes the problem of a bottom electrode and dielectric layer which chemically interact to form a silicon oxide layer in series or below the desired dielectric layer.

    摘要翻译： 描述了一种电容器和制造方法，其包括半导体衬底，形成在衬底上或衬底中的底部电极，钡或硅酸铅的电介质层和顶部电极。 钡或硅酸铅和诸如钡或钛酸铅的高介电常数材料的夹层电介质可以包括电介质。 硅酸盐层可以通过蒸发和扩散，离子注入或电镀和扩散钡或铅而形成。 高ε介电常数材料可以通过溶胶凝胶沉积，金属有机化学气相沉积或溅射形成。 本发明克服了底部电极和电介质层的问题，化学相互作用以形成串联或低于所需电介质层的氧化硅层。

    STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME
    8.
    发明申请
    STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME 审中-公开
    使用双BELAYER处理方案的互连结构CU LINER

    公开(公告)号：US20090098728A1

    公开(公告)日：2009-04-16

    申请号：US11870649

    申请日：2007-10-11

    申请人： Stephan Grunow ,  Thomas McCarroll Shaw ,  Andrew H. Simon ,  Chih-Chao Yang ,  Tiblor Bolom ,  James Werking

    发明人： Stephan Grunow ,  Thomas McCarroll Shaw ,  Andrew H. Simon ,  Chih-Chao Yang ,  Tiblor Bolom ,  James Werking

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76846 ,  H01L21/76805 ,  H01L21/76865

    摘要： The disclosed method forms a via between metallization layers in a semiconductor structure by patterning an insulator layer overlying a first metallization layer to include a via opening. The method lines the via opening with TaN and Ta liners and then sputter etches the via opening deeper through the TaN and Ta liners into the first metallization layer. After sputter etching, the method then lines the via opening with second TaN and Ta liners. Next, the method deposits a conductor into the via opening, thereby connecting the first and second metallization layers.

    摘要翻译： 所公开的方法通过图案化覆盖在第一金属化层上的绝缘体层以包括通孔开口在半导体结构中的金属化层之间形成通孔。 该方法用TaN和Ta衬垫将通孔开口排列，然后通过TaN和Ta衬垫将通孔开口溅射到第一金属化层中。 在溅射蚀刻之后，该方法然后将通孔与第二TaN和Ta衬垫分开。 接下来，该方法将导体沉积到通孔开口中，从而连接第一和第二金属化层。