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1.发明授权Semiconductor structure having heterogenous silicide regions having titanium and molybdenum 失效具有异质硅化物区域的具有钛和钼的半导体结构公开(公告)号：US06512296B1
公开(公告)日：2003-01-28
申请号：US09636325
申请日：2000-08-10
IPC分类号： H01L2348
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28518 , H01L21/28568 , H01L21/823418 , H01L21/823443 , H01L29/456
摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.
摘要翻译： 在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。 然后将钛沉积在半导体衬底（10）上。 半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅 该基板在高电阻率C49晶相中形成硅化钛。 在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。
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2.发明授权Semiconductor structure having heterogeneous silicide regions and method for forming same 失效具有异质硅化物区域的半导体结构及其形成方法公开(公告)号：US06187617B1
公开(公告)日：2001-02-13
申请号：US09363558
申请日：1999-07-29
IPC分类号： H01L21336
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28518 , H01L21/28568 , H01L21/823418 , H01L21/823443 , H01L29/456
摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.
摘要翻译： 在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。 然后将钛沉积在半导体衬底（10）上。 半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅 该基板在高电阻率C49晶相中形成硅化钛。 在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。
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公开(公告)号：US06441410B2
公开(公告)日：2002-08-27
申请号：US09809014
申请日：2001-03-16
IPC分类号： H01L2980
CPC分类号： H01L28/24 , H01L21/28518 , H01L27/0738 , H01L29/41725 , H01L29/435 , H01L29/665
摘要： The current density profile in the conduction channel of a field effect transistor is controlled and thermal gradients are limited under extreme operating conditions by providing lateral resistive ballasting at the source/drain regions adjacent the conduction channel. A distributed resistance is formed by inhibiting conversion of a region of deposited salicide from a high resistance phase state to a low resistance phase state through formation of the deposit with a width or area less than a critical dimension.
摘要翻译： 控制场效应晶体管的导通通道中的电流密度分布，并通过在邻近导通通道的源极/漏极区域提供横向电阻镇流，在极端工作条件下限制热梯度。 通过形成具有小于临界尺寸的宽度或面积的沉积物，通过抑制沉积的自对准硅化物的区域从高电阻相位状态转变为低电阻相位状态来形成分布电阻。
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4.发明授权公开(公告)号：US06268286B1
公开(公告)日：2001-07-31
申请号：US09495499
申请日：2000-02-01
IPC分类号： H01L2144
CPC分类号： H01L28/24 , H01L21/28518 , H01L27/0738 , H01L29/41725 , H01L29/435 , H01L29/665
摘要： The current density profile in the conduction channel of a field effect transistor is controlled and thermal gradients are limited under extreme operating conditions by providing lateral resistive ballasting at the source/drain regions adjacent the conduction channel. A distributed resistance is formed by inhibiting conversion of a region of deposited salicide from a high resistance phase state to a low resistance phase state through formation of the deposit with a width or area less than a critical dimension.
摘要翻译： 控制场效应晶体管的导通通道中的电流密度分布，并通过在邻近导通通道的源极/漏极区域提供横向电阻镇流，在极端工作条件下限制热梯度。 通过形成具有小于临界尺寸的宽度或面积的沉积物，通过抑制沉积的自对准硅化物的区域从高电阻相位状态转变为低电阻相位状态来形成分布电阻。
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5.发明授权Thermal conductivity enhanced semiconductor structures and fabrication processes 有权热导率增强的半导体结构和制造工艺公开(公告)号：US06288426B1
公开(公告)日：2001-09-11
申请号：US09514106
申请日：2000-02-28
IPC分类号： H01L2900
CPC分类号： H01L29/78648 , H01L21/76264 , H01L21/76286 , H01L21/763 , H01L23/3677 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.
摘要翻译： 在选择的电子部件的制造期间，在基板上的选定位置处形成硅。 介电分离区形成在顶层硅层内，并填充有导热材料。 衬里材料可以在沉积导热材料之前任选地沉积。 在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。
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6.发明授权Method of forming a semiconductor diode with depleted polysilicon gate structure 有权形成具有耗尽的多晶硅栅结构的半导体二极管的方法公开(公告)号：US06232163B1
公开(公告)日：2001-05-15
申请号：US09362549
申请日：1999-07-28
IPC分类号： H01L218238
CPC分类号： H01L27/0811 , H01L29/7391 , H01L2924/0002 , H01L2924/00
摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.
摘要翻译： 用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。 优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。 阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。 施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。 本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。 或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。 可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。
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公开(公告)号：US6034388A
公开(公告)日：2000-03-07
申请号：US79846
申请日：1998-05-15
IPC分类号： H01L21/334 , H01L21/762 , H01L21/8238 , H01L27/06 , H01L27/12 , H01L29/94 , H01L29/76
CPC分类号： H01L29/66181 , H01L21/76237 , H01L21/76264 , H01L21/823842 , H01L21/82385 , H01L27/0629 , H01L27/1203 , H01L29/94 , H01L21/76283 , Y10S257/907
摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.
摘要翻译： 一种包括半导体衬底的电路元件。 第一导电类型的阱区形成在衬底的表面中。 在基板上形成电介质膜。 在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。 栅极导体由多晶硅膜形成。 栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 在栅极导体的每一侧上形成多晶硅边缘隔离物。 第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。 多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。 第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。 应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。
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公开(公告)号：US06429066B1
公开(公告)日：2002-08-06
申请号：US09465097
申请日：1999-12-16
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L21/76237 , H01L21/76264 , H01L21/76283 , H01L21/823842 , H01L21/82385 , H01L27/0629 , H01L27/1203 , H01L29/94 , Y10S257/907
摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.
摘要翻译： 一种包括半导体衬底的电路元件。 第一导电类型的阱区形成在衬底的表面中。 在基板上形成电介质膜。 在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。 栅极导体由多晶硅膜形成。 栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 在栅极导体的每一侧上形成多晶硅边缘隔离物。 第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。 多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。 第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。 应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。
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公开(公告)号：US5998848A
公开(公告)日：1999-12-07
申请号：US157003
申请日：1998-09-18
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/762 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/6659 , H01L21/28105 , H01L21/28123 , H01L21/76224 , H01L29/4238 , H01L29/4983 , Y10S438/919
摘要： A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.
摘要翻译： 具有减小的拐角设备问题的场效应晶体管包括形成在衬底中的源极和漏极区域，源极和漏极区域之间的沟道区域，邻近源极，沟道和漏极区域的衬底中的隔离区域; 以及在沟道区域上具有栅极掺杂剂并由栅极电介质分离的栅极。 隔离区域定义了通道与隔离区域之间的接口的拐角区域。 栅极包括耗尽栅极掺杂剂的区域，并且至少与沟道区域和隔离区域重叠，使得栅极导体层的耗尽部分之下的沟道拐角区域的电压阈值与角区域之间的沟道区域相比增加 。 MOSFET栅极“拐角”上掺杂浓度降低的场效应晶体管具有改善的边缘电压容差。 该结构具有改善的边缘电介质击穿和较低的MOSFET栅极引起的漏极泄漏（GIDL）。 该结构适用于模拟应用，混合耐压电路和静电（ESD）网络。
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10.发明授权公开(公告)号：US06352905B1
公开(公告)日：2002-03-05
申请号：US09702787
申请日：2000-11-01
IPC分类号： H01L2176
CPC分类号： H01L21/7624
摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
摘要翻译： 用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体 （第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。
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