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1.发明授权
公开(公告)号：US5898317A
公开(公告)日：1999-04-27
申请号：US772736
申请日：1996-12-23
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/17772 , H03K19/1776 , H03K19/1778
摘要： A ferroelectric memory array (20) monolithically integrated with a field programmable gate array (32) into a semiconductor circuit (10). The ferroelectric memory array (20) is suitable for a semiconductor manufacturer to program the configuration data that is used in the field programmable gate array (32) prior to shipment and installation in an electronic system. The memory array (20) provides the data that configures the field programmable gate array (32) for functionality of the Configurable Logic Blocks (CLBs) in the field programmable gate array (32). Should the field programmable gate array (32) circuit lose power, the non-volatile memory array (20) provides a shift register (26) with the data to reconfigure the field programmable gate array (32).
摘要翻译： 与现场可编程门阵列（32）单片集成到半导体电路（10）中的铁电存储器阵列（20）。 铁电存储器阵列（20）适用于半导体制造商，以在电子系统中装运和安装之前编程在现场可编程门阵列（32）中使用的配置数据。 存储器阵列（20）为现场可编程门阵列（32）中的可配置逻辑块（CLB）的功能提供配置现场可编程门阵列（32）的数据。 如果现场可编程门阵列（32）电路失去功率，则非易失性存储器阵列（20）为移位寄存器（26）提供数据以重新配置现场可编程门阵列（32）。
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公开(公告)号：US5923184A
公开(公告)日：1999-07-13
申请号：US772744
申请日：1996-12-23
IPC分类号： H03K19/08 , H03K19/094 , H03K19/173
CPC分类号： H03K19/08
摘要： Ferroelectric transistors are combined with MOSFETs to perform logic functions. The logic functions include a non-volatile ferroelectric latch (30), a clocked non-volatile ferroelectric latch (50), a programmable switch (60), an edge-triggered complementary flip-flop (78), a tri-state logic circuit (80), a ferroelectric logic NAND-gate (100), a clocked ferroelectric logic NAND-gate (140), and a programmable logic function (150). The programmable logic function (150) includes a programming terminal (156) to select between a NOR-gate function and a NAND-gate function.
摘要翻译： 铁电晶体管与MOSFET组合起来执行逻辑功能。 逻辑功能包括非易失性铁电锁存器（30），时钟非易失性铁电锁存器（50），可编程开关（60），边沿触发互补触发器（78），三态逻辑电路 （80），铁电逻辑NAND门（100），时钟铁电逻辑NAND门（140）和可编程逻辑功能（150）。 可编程逻辑功能（150）包括用于在非门功能和非门功能之间进行选择的编程终端（156）。
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公开(公告)号：US6025735A
公开(公告)日：2000-02-15
申请号：US772735
申请日：1996-12-23
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/1736 , H03K19/17748 , H03K19/17756
摘要： A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.
摘要翻译： 现场可编程门阵列（FPGA）中的开关网络（22），其作为编程晶体管（34）和铁电晶体管（32）的组合工作。 编程晶体管（34）被选择为将极化电压传递到铁电晶体管（32）的栅极端子，用于将铁电晶体管（32）编程为导通状态。 铁电晶体管（32）用作非易失性锁存和通过装置，以提供链接多个可配置逻辑块（CLB）的电互连路径。 编程晶体管（34）被选择为将去极化电压传递到铁电晶体管（32）的栅极端子，用于将铁电晶体管（32）编程为截止状态。
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4.发明授权Thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat 失效热电发电机及利用潜热蒸汽在蒸汽动力循环中产生热电功率的方法公开(公告)号：US06367261B1
公开(公告)日：2002-04-09
申请号：US09703072
申请日：2000-10-30
IPC分类号： F01K1700
摘要： A thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat including a condenser, a heat source, such as steam, and at least one thermoelectric module. The condenser includes a plurality of condenser tubes each having included therein a heat extractor. The heat source is in communication with the condenser and is characterized as providing thermal energy to the condenser. The at least one thermoelectric module, including a plurality of thermoelectric elements, is positioned in communication with at least one of the plurality of condenser tubes so that thermal energy flows through the thermoelectric elements thereby generating electrical power.
摘要翻译： 一种热电发电机和利用包括冷凝器，热源（例如蒸汽）和至少一个热电模块的潜热蒸汽热在蒸汽动力循环中产生热电功率的方法。 冷凝器包括多个冷凝管，每个冷凝管每个都包括一个散热器。 热源与冷凝器连通，其特征在于向冷凝器提供热能。 包括多个热电元件的至少一个热电模块被定位成与多个冷凝器管中的至少一个连通，使得热能流过热电元件从而产生电力。
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5.发明授权
公开(公告)号：US6097047A
公开(公告)日：2000-08-01
申请号：US70063
申请日：1998-04-30
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/8234 , H01L29/1079 , H01L29/78391 , H01L29/78603 , H01L29/78645
摘要： A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).
摘要翻译： 铁电半导体器件（10）和制造铁电半导体器件（10）的方法。 铁电半导体装置（10）由具有夹在基板（13）和硅层（16）之间的铁电材料层（14）的基板（11）制成。 在硅的层（16）上形成栅极结构（24）。 源极区域形成在与栅极结构（24）的一侧相邻的硅的层（16）的一部分中，并且漏极区域形成在邻近栅极的相对侧的硅层（16）的一部分中 结构（24）。
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6.发明授权
公开(公告)号：US5767543A
公开(公告)日：1998-06-16
申请号：US714715
申请日：1996-09-16
IPC分类号： H01L21/02 , H01L21/285 , H01L21/314 , H01L21/316 , H01L29/51 , H01L29/788 , G11C11/22
CPC分类号： H01L28/56 , H01L21/2855 , H01L21/28556 , H01L21/31691 , H01L29/516
摘要： A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.
摘要翻译： 层状铋强电介质结构（12）和形成铋层状铁电体结构（12）的方法。 形成与单晶半导体材料（11）紧密接触的铋单层（12A）。 在铋的单层（12A）上生长分层的铁电材料（12），使得铋的单层（12A）成为层状铁电体（12）的一部分。 铁电材料（12）形成不是纯钙钛矿的层状铁电体材料，其中在单晶半导体材料（11）和铋单层（12A）之间的界面处的晶体结构基本上相同。
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公开(公告)号：US06022410A
公开(公告)日：2000-02-08
申请号：US144921
申请日：1998-09-01
申请人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Daniel S. Marshall , Jerald A. Hallmark , Jonathan K. Abrokwah
发明人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Daniel S. Marshall , Jerald A. Hallmark , Jonathan K. Abrokwah
IPC分类号： H01L21/203 , C30B23/02 , C30B29/10 , C30B23/00
摘要： A method of forming a thin silicide layer on a silicon substrate 12 including heating the surface of the substrate to a temperature of approximately 500.degree. C. to 750.degree. C. and directing an atomic beam of silicon 18 and an atomic beam of an alkaline-earth metal 20 at the heated surface of the substrate in a molecular beam epitaxy chamber at a pressure in a range below 10.sup.-9 Torr. The silicon to alkaline-earth metal flux ratio is kept constant (e.g. Si/Ba flux ratio is kept at approximately 2:1) so as to form a thin alkaline-earth metal silicide layer (e.g. BaSi.sub.2) on the surface of the substrate. The thickness is determined by monitoring in situ the surface of the single crystal silicide layer with RHEED and terminating the atomic beam when the silicide layer is a selected submonolayer to one monolayer thick.
摘要翻译： 一种在硅衬底12上形成薄硅化物层的方法，包括将衬底的表面加热至约500℃至750℃的温度，并引导硅18的原子束和碱性电子束的原子束， 在分子束外延室中的衬底的加热表面处的压力在10-9乇以下的地球金属20。 将硅与碱土金属的通量比保持恒定（例如，Si / Ba通量比保持在约2:1），以在衬底的表面上形成薄的碱土金属硅化物层（例如BaSi 2）。 通过用RHEED原位监测单晶硅化物层的表面并且当硅化物层是选择的亚单层至一个单层厚度时终止原子束来确定厚度。
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8.发明授权
公开(公告)号：US5888296A
公开(公告)日：1999-03-30
申请号：US956622
申请日：1997-09-29
IPC分类号： H01L21/02 , H01L21/285 , H01L21/314 , H01L21/316 , H01L29/51 , C30B23/00
CPC分类号： H01L28/56 , H01L21/2855 , H01L21/28556 , H01L21/31691 , H01L29/516
摘要： A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.
摘要翻译： 层状铋铁电体结构（12）和形成铋层状铁电体结构（12）的方法。 形成与单晶半导体材料（11）紧密接触的铋单层（12A）。 在铋的单层（12A）上生长分层的铁电材料（12），使得铋的单层（12A）成为层状铁电体（12）的一部分。 铁电材料（12）形成不是纯钙钛矿的层状铁电体材料，其中在单晶半导体材料（11）和铋单层（12A）之间的界面处的晶体结构基本上相同。
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公开(公告)号：US5846847A
公开(公告)日：1998-12-08
申请号：US743769
申请日：1996-11-07
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10 , H01L29/78 , H01L29/786 , H01G7/06 , H01L21/8239
CPC分类号： H01L29/66772 , H01L21/8234 , H01L29/1079 , H01L29/78391 , H01L29/78603 , H01L29/78645
摘要： A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).
摘要翻译： 铁电半导体器件（10）和制造铁电半导体器件（10）的方法。 铁电半导体装置（10）由具有夹在基板（13）和硅层（16）之间的铁电材料层（14）的基板（11）制成。 在硅的层（16）上形成栅极结构（24）。 源极区域形成在与栅极结构（24）的一侧相邻的硅的层（16）的一部分中，并且漏极区域形成在邻近栅极的相对侧的硅层（16）的一部分中 结构（24）。
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公开(公告)号：US06472278B1
公开(公告)日：2002-10-29
申请号：US09679184
申请日：2000-10-04
IPC分类号： H01L21336
CPC分类号： H01L29/66568 , H01L29/4975 , H01L29/517 , H01L29/78 , H01L29/7838
摘要： A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.
摘要翻译： 一种制造场效应晶体管的方法，包括在邻近表面的半导体衬底结构中掺杂连续覆盖层，以包括与源极区域间隔开的源极区域和漏极区域。 高介电常数绝缘体层位于覆盖连续覆盖层的半导体衬底结构的表面上，以限定源区和漏区之间的栅极区。 选择绝缘体层上的栅极接触以提供消耗绝缘体层下方的掺杂层的功函数差异。 此外，掺杂层深度和剂量被设计成使得掺杂层通过栅极接触和半导体衬底的选择的功函数差耗尽在绝缘体层之下。
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