利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

222 条记录 (耗时 0.034 秒)

    METAL-OXIDE-SEMICONDUCTOR (MOS) VARACTORS AND METHODS OF FORMING MOS VARACTORS
    1.
    发明申请
    METAL-OXIDE-SEMICONDUCTOR (MOS) VARACTORS AND METHODS OF FORMING MOS VARACTORS 审中-公开
    金属氧化物半导体（MOS）变压器及形成MOS电容器的方法

    公开(公告)号：US20080149983A1

    公开(公告)日：2008-06-26

    申请号：US11613471

    申请日：2006-12-20

    申请人： Robert Mark Rassel ,  Douglas Duane Coolbaugh ,  Zhong-Xiang He ,  Ebenezer E. Eshun ,  David S. Collins ,  Douglas Brian Hershberger

    发明人： Robert Mark Rassel ,  Douglas Duane Coolbaugh ,  Zhong-Xiang He ,  Ebenezer E. Eshun ,  David S. Collins ,  Douglas Brian Hershberger

    IPC分类号： H01L29/94 ,  H01L21/20 ,  H01L21/336

    CPC分类号： H01L29/93 ,  H01L29/94

    摘要： MOS varactor having an entire accumulation and depletion regime of its CV characteristic curve in one bias regime (negative or positive). The MOS varactor may comprise a gate electrode, a well region of semiconductor material having a first conductivity type (e.g., p-type), contact regions to the well region that comprise heavily doped semiconductor material of the first conductivity type (e.g., p+-type), and a Schottky junction formed between the gate and contact regions. The Schottky junction may be formed by spacing the contact regions away from the gate electrode and siliciding the substrate surface. The gate electrode may be formed from semiconductor material of a second conductivity type (e.g., n-type) opposite to the first conductivity type, thus changing the flat band voltage of the MOS varactor and shifting accumulation and depletion regime of the CV characteristic curve in one bias regime, such as the negative bias regime.

    摘要翻译： MOS变容二极管在一个偏置方式（负或正）中具有其CV特性曲线的整体累积和耗尽方式。 MOS变容二极管可以包括栅电极，具有第一导电类型（例如，p型）的半导体材料的阱区，包括第一导电类型的重掺杂半导体材料的阱区的接触区域（例如，p < SUP + +型）和在栅极和接触区域之间形成的肖特基结。 肖特基结可以通过将接触区域与栅电极隔开并使衬底表面硅化而形成。 栅电极可以由与第一导电类型相反的第二导电类型（例如，n型）的半导体材料形成，从而改变MOS变容二极管的平带电压以及CV特性曲线的转移累积和耗尽状态 一种偏见制度，如负偏见制度。

    Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric
    3.
    发明授权
    Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric 有权
    将MIM电容器与形成在阱区中并具有高k电介质的板集成

    公开(公告)号：US07361950B2

    公开(公告)日：2008-04-22

    申请号：US11162471

    申请日：2005-09-12

    申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

    发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L28/40

    摘要： A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by sidewall spacers.

    摘要翻译： 在具有顶表面并且包括形成在从浅沟槽隔离（STI）区域中选择的表面中的区域和具有与半导体衬底共面的外表面的掺杂阱的半导体衬底上形成MIM电容器。 电容器底板是形成在半导体衬底中的STI区域上的下电极或由可能具有硅化物表面的在半导体衬底的顶表面中形成的掺杂阱形成的下电极。 电容器HiK电介质层形成在下板上或上。 在电容器下板上方的HiK电介质层上形成电容器第二板。 可以在第二板的上方形成具有顶板的双电容器结构，其中通过侧壁间隔件连接到被第二板保护的下板的通孔。

    MIM capacitor and method of making same
    5.
    发明授权
    MIM capacitor and method of making same 有权
    MIM电容器及其制作方法

    公开(公告)号：US07488643B2

    公开(公告)日：2009-02-10

    申请号：US11425549

    申请日：2006-06-21

    申请人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

    发明人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/60

    摘要： A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader plate having a top surface, a bottom surface and sidewalls; and a dielectric block comprising one or more dielectric layers the dielectric block having a top surface, a bottom surface and sidewalls, the top surface of the dielectric block in physical contact with the bottom surface of the upper plate, the bottom surface of the dielectric block over the top surface of the spreader plate, the sidewalls of the upper plate and the dielectric block essentially co-planer.

    摘要翻译： 一种MIM电容器及其制造方法。 该装置包括包括一个或多个导电层的上板，上板具有顶表面，底表面和侧壁; 包括一个或多个导电层的扩展板，所述扩展板具有顶表面，底表面和侧壁; 以及介电块，其包括一个或多个电介质层，介电块具有顶表面，底表面和侧壁，介电块的顶表面与上板的底表面物理接触，介质块的底表面 在扩展板的顶表面上方，上板和介质块的侧壁基本上是共平面的。

    MIM CAPACITOR AND METHOD OF MAKING SAME
    8.
    发明申请
    MIM CAPACITOR AND METHOD OF MAKING SAME 有权
    MIM电容器及其制造方法

    公开(公告)号：US20070296085A1

    公开(公告)日：2007-12-27

    申请号：US11425549

    申请日：2006-06-21

    申请人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

    发明人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L28/60

    摘要： A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader plate having a top surface, a bottom surface and sidewalls; and a dielectric block comprising one or more dielectric layers the dielectric block having a top surface, a bottom surface and sidewalls, the top surface of the dielectric block in physical contact with the bottom surface of the upper plate, the bottom surface of the dielectric block over the top surface of the spreader plate, the sidewalls of the upper plate and the dielectric block essentially co-planer.

    摘要翻译： 一种MIM电容器及其制造方法。 该装置包括包括一个或多个导电层的上板，上板具有顶表面，底表面和侧壁; 包括一个或多个导电层的扩展板，所述扩展板具有顶表面，底表面和侧壁; 以及介电块，其包括一个或多个电介质层，介电块具有顶表面，底表面和侧壁，介电块的顶表面与上板的底表面物理接触，介质块的底表面 在扩展板的顶表面上方，上板和介质块的侧壁基本上是共平面的。