公开(公告)号：US5574942A

公开(公告)日：1996-11-12

申请号：US602254

申请日：1996-02-15

申请人： Robert P. Colwell ,  David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Stephen M. Coward ,  Grace C. Chen

发明人： Robert P. Colwell ,  David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Stephen M. Coward ,  Grace C. Chen

IPC分类号： G06F9/302 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30014 ,  G06F9/3885

摘要： A hybrid execution unit for executing miscellaneous instructions in a single clock cycle. The execution unit receives either integer or floating point data, and performs manipulations of two incoming sources to produce a result source in conjunction with existing integer and floating point execution units.

摘要翻译： 一种混合执行单元，用于在单个时钟周期内执行各种指令。 执行单元接收整数或浮点数据，并执行两个输入源的操作以产生结合现有整数和浮点执行单元的结果源。

公开(公告)号：US5584037A

公开(公告)日：1996-12-10

申请号：US571377

申请日：1995-12-13

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度和推测执行的微处理器的应用。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5564111A

公开(公告)日：1996-10-08

申请号：US315833

申请日：1994-09-30

申请人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

发明人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/38 ,  G06F11/00 ,  G06F12/10 ,  G06F11/34

CPC分类号： G06F9/3865 ,  G06F11/0751 ,  G06F12/1027 ,  G06F9/3842 ,  G06F2212/684

摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.

摘要翻译： 描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。 在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。 所存储的信息包括指令的线性地址和识别指令年龄的信息。 除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。 在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。 在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。 然后，一个分支被带入微码。 微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。 系统被刷新，微代码仅对实际退出的故障指令执行。 因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。 本文描述了方法和装置实现。

公开(公告)号：US5987600A

公开(公告)日：1999-11-16

申请号：US851140

申请日：1997-05-05

申请人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

发明人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3842 ,  G06F9/3863

摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

摘要翻译： 用于协调处理器中的异常的方法和电路。 处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。 处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。 如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

公开(公告)号：US5627985A

公开(公告)日：1997-05-06

申请号：US177244

申请日：1994-01-04

申请人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

发明人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

IPC分类号： G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

摘要翻译： 一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果 或浮点运算，具体取决于寄存器。 重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。 退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。

公开(公告)号：US5604878A

公开(公告)日：1997-02-18

申请号：US513679

申请日：1995-08-01

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

摘要翻译： 执行可能参与回写冲突的功能单位的管道延长，以避免冲突。 提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。 当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。 冲突解决后，延长给定功能单位管道的指示将被撤销。 多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

公开(公告)号：US5913050A

公开(公告)日：1999-06-15

申请号：US735048

申请日：1996-10-22

申请人： Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth

发明人： Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F12/06 ,  G06F9/26

CPC分类号： G06F9/3804 ,  G06F9/30054

摘要： This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address. The next instruction is fetched at the corrected linear address.

摘要翻译： 本发明通过首先从分支指令的线性目的地地址中减去分段基地址来生成虚拟目的地地址来克服地址大小向后兼容性问题。 假设分支指令目标地址是n位长，m个最高有效位。 期望在n比特处理器中为使用大小（n-m）比特的指令地址字段为处理器编写的分支指令代码提供向后兼容性。 在获得虚拟地址之后，如果m个最高有效位中的任何一个非零，则将这些m位设置为零，从而生成校正的虚拟地址。 如果需要这种兼容性校正，则清除信号被断言以清除在分支指令被取出之后被取出的指令导致的处理器的所有状态。 校正的虚拟地址被加回到段基地址以产生校正的线性地址。 下一条指令是在校正的线性地址处获取的。

公开(公告)号：US5809271A

公开(公告)日：1998-09-15

申请号：US518563

申请日：1995-08-23

申请人： Robert P. Colwell ,  Atiq Bajwa ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth

发明人： Robert P. Colwell ,  Atiq Bajwa ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/26

CPC分类号： G06F9/3865 ,  G06F9/322 ,  G06F9/3844

摘要： A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.

摘要翻译： 提供了一种用于处理微处理器中指令控制流程变化的简化方法和装置。 处理器不是试图立即实现指令流程的改变，而是根据流量控制指示符首先识别流程将从预测指令流重定向到正确的指令流。 流量控制指示器可以附接到沿着流水线向下流动的指令或作为管道中的单独指令插入。 管道被清除由不遵循正确指令流程的指令创建的状态，即在引起流量变化的指令之后被错误地取出的指令。 流量控制指示器所示的流量变化在后面的流水线中实现。

公开(公告)号：US5778245A

公开(公告)日：1998-07-07

申请号：US204861

申请日：1994-03-01

申请人： David B. Papworth ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert P. Colwell ,  Michael A. Fetterman ,  Shantanu R. Gupta ,  James S. Griffith

发明人： David B. Papworth ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert P. Colwell ,  Michael A. Fetterman ,  Shantanu R. Gupta ,  James S. Griffith

IPC分类号： G06F9/38 ,  G06F9/50 ,  G06F15/82

CPC分类号： G06F9/5016 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.

摘要翻译： 一种用于以有效方式动态地将微处理器资源的条目分配给特定指令以有效利用缓冲器大小和资源的方法和装置。 流水线和超标量微处理器能够推测性地执行指令并进行无序处理。 微处理器内的资源包括存储缓冲器，加载缓冲器，重新排序缓冲器和保留站。 重排序缓冲器包含较大的一组物理寄存器，并且还包含与推测指令相关的信息，并且保留站包括与待执行的指令相关的信息。 加载缓冲区仅分配给加载指令，对从分配管理到指令退出的指令有效。 存储缓冲区仅被分配用于存储指令，并且对于分配的指令有效以存储性能。 保留站被分配给大多数指令，并且对于从分配到指令分派的指令是有效的。 重新排序缓冲区被分配给所有指令，并且对于从分配到退休的给定指令是有效的。 在保留站不存在的情况下顺序地分配负载缓冲器，存储缓冲器和重排序缓冲器。 动态执行资源分配（根据操作需要），而不是作为每个操作附加的一整套资源。 使用上述分配方案，可以实现微处理器资源的高效利用。

公开(公告)号：US5584038A

公开(公告)日：1996-12-10

申请号：US633905

申请日：1996-04-17

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度的推测执行的微处理器的应用程序。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。