-
公开(公告)号：US06577481B2
公开(公告)日：2003-06-10
申请号：US10052845
申请日：2001-11-02
IPC分类号： H02H900
CPC分类号： H02H9/046
摘要： The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node 10; a bottom one Q1 of the at least two bipolar transistors coupled to a common node 12; at least two resistors R1-Rn coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one R1 of the at least two resistors coupled between a base of the bottom one Q1 of the at least two bipolar transistors and the common node 12.
-
公开(公告)号：US06784496B1
公开(公告)日：2004-08-31
申请号：US09668999
申请日：2000-09-25
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.
摘要翻译： 集成在接口电路中的CDM钳位电路，它在集成电路上进行保护。 通常，集成的CDM钳位电路和接口电路彼此相邻并且共享公共器件元件或元件，因此不需要金属互连。 因为没有互连，寄生电阻和电感也被最小化或从电路中消除，从而减少或消除过大的电压降。 优选地，CDM钳位电路通过使两个电路共享相同的硅源区域而被集成到其正在保护的电路中。 在优选实施例的输入电路中，相同的扩散区域是输入晶体管及其相关联的CDM钳位晶体管的源极。
-
公开(公告)号：US08384127B1
公开(公告)日：2013-02-26
申请号：US09498677
申请日：2000-02-07
IPC分类号： H01L29/747
CPC分类号： H01L27/0277 , H01L27/0274 , H01L29/0692 , H01L29/1083 , H01L29/41758 , H01L29/4238 , H01L29/78
摘要： A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
-
公开(公告)号：US06424013B1
公开(公告)日：2002-07-23
申请号：US09586637
申请日：2000-06-05
IPC分类号： H01L2362
CPC分类号： H01L27/0277
摘要： A protection circuit is designed with an external terminal (300), a reference terminal (126) and a substrate (342). A semiconductor body (338) is formed by an isolation region (332, 340) formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal (354) connected to a common control terminal (321) and a respective current path connected between the external terminal and the reference terminal. A capacitor (314) is connected between the semiconductor body and the external terminal. A resistor (318) is connected between the semiconductor body and the reference terminal.
摘要翻译： 保护电路设计有外部端子（300），参考端子（126）和基板（342）。 半导体本体（338）由形成在衬底和半导体本体之间的隔离区（332,340）形成，从而包围半导体本体。 在半导体本体中形成多个晶体管。 每个晶体管具有连接到公共控制端子（321）的相应控制端子（354）和连接在外部端子与参考端子之间的相应电流路径。 电容器（314）连接在半导体本体和外部端子之间。 电阻器（318）连接在半导体本体和参考端子之间。
-
5.发明授权ESD protection circuit using zener diode and interdigitated NPN transistor 失效ESD保护电路采用齐纳二极管和交叉NPN晶体管
公开(公告)号：US5850095A
公开(公告)日：1998-12-15
申请号：US719195
申请日：1996-09-24
CPC分类号： H01L27/0248
摘要： The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically
摘要翻译： 本发明提供了一种高效率的ESD电路，其通过均匀地激活包含整流齐纳二极管的晶体管结构的多个发射极指，需要更少的空间。 齐纳二极管能够将保护电路触发阈值从大约18伏降低到大约7伏。 该方法使信号路径的串联阻抗最小化，从而使得NPN结构特别适用于保护双极和CMOS输入和输出缓冲器。 本发明的ESD电路提供对当前和未来考虑的亚微米双极/ BiCMOS电路的输入和输出电路所需的相对较低的并联电容（通常<0.5pF）和串联电阻（通常<0.5欧姆） 过程。
-
6.发明授权Stacked silicon-controlled rectifier having a low voltage trigger and adjustable holding voltage for ESD protection 失效堆叠的可控硅整流器具有低电压触发和可调保持电压用于ESD保护
公开(公告)号：US6016002A
公开(公告)日：2000-01-18
申请号：US993820
申请日：1997-12-18
IPC分类号： H01L29/74 , H01L23/60 , H01L27/02 , H02H7/20 , H02H9/04 , H05F3/02 , H01L23/62 , H01L29/00 , H01L31/111
CPC分类号： H01L27/0262 , H01L27/0266 , H01L2924/0002
摘要： An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground. The SCR (68) remains latched until the voltage applied to the signal path (69) falls beneath a holding voltage of the SCR (68). A plurality of the SCRs (126, 128) may be connected in series, such that the overall holding voltage for the series of SCRs (126, 128) is approximately equal to the sum of the individual holding voltages for the SCRs (126, 128), which overall holding voltage is greater than the trigger voltage. Preferably, the SCR (68) is isolated from the P substrate (92) by a P-N junction which is provided by disposing the SCR (68) within an N-tank (98).
摘要翻译： 提供了用于保护集成电路（62）抵抗ESD事件的SCR（68），其具有响应于施加到集成电路（62）的功率而被自动调整到不同触发电压电平的触发电压。 提供增强型P沟道晶体管（78）用于确定触发电压。 当工作电源未被施加到集成电路（62）时，P沟道晶体管（78）阈值电压确定触发SCR（68）的电压。 当工作电源施加到集成电路（62）时，工作电压被施加到P沟道晶体管（78）的栅极，然后P沟道晶体管（78）的工作电压和阈值电压 确定SCR（68）的触发电压。 然后，形成SCR（68）的PNP和NPN晶体管对（76,80）被锁存以将受保护的信号路径（69）分流到地。 SCR（68）保持锁存，直到施加到信号路径（69）的电压落在SCR（68）的保持电压以下。 多个SCR（126,128）可以串联连接，使得SCR系列（126,128）的整体保持电压近似等于SCR的各个保持电压之和（126,128 ），其总保持电压大于触发电压。 优选地，SCR（68）通过将SCR（68）设置在N-罐（98）内而提供的P-N结与P基板（92）隔离。
-
公开(公告)号：US5982217A
公开(公告)日：1999-11-09
申请号：US25916
申请日：1998-02-19
CPC分类号： H01L27/027 , H01L27/0259
摘要： A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.
摘要翻译： 为先进的非硅化物/硅化物亚微米CMOS工艺提供了新颖的PNP驱动NMOS（PDNMOS）保护方案。 PNP晶体管的发射极和保护NMOS漏极漏极连接到由PDNMOS提供ESD保护的I / O焊盘。 PNP晶体管的集电极和保护NMOS晶体管的栅极通过电阻连接到地。 保护NMOS晶体管的源极接地。 PNP晶体管的基极连接到集成电路的电容器或寄生电容器。
-
8.发明授权System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing 有权使用横向PNP或PMOS或两者用于衬底偏置的静电放电保护的系统和方法公开(公告)号：US06628493B1
公开(公告)日：2003-09-30
申请号：US09546988
申请日：2000-04-11
IPC分类号： H02H900
CPC分类号： H01L27/027 , H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1). Alternatively, the protective circuit (40) also may use a PMOS traisistor (P1), or a PMOS transistor (P1) in combination with the lateral NPN transistor (T1), coupled to the input element (20) and to the lateral NPN transistor (T1). The PMOS transistor (P1) is operable to aid in raising the potential of the base of the lateral NPN transistor (T1).
摘要翻译： 本发明包括提供静电放电保护的系统和方法。 在本发明的一个实施例中，包括至少一个输入元件（20）的集成电路（10）由保护电路（40）保护。 保护电路（40）可操作以保护集成电路（10）免受静电放电所造成的损坏，并可与输入元件（20）耦合。 保护电路（40）包括耦合到输入元件（20）的横向NPN晶体管（T1），并且可操作以在输入元件电压超过阈值时启动，阈值大于或等于耦合到该电路的电路的正常工作电压 输入元件（20）。 保护电路（40）还可以包括耦合到输入元件（20）和横向NPN晶体管（T1）的横向PNP晶体管（T2）。 横向PNP晶体管（T2）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。 或者，保护电路（40）还可以使用与横向NPN晶体管（T1）组合的PMOS晶体管（P1）或PMOS晶体管（P1），耦合到输入元件（20）和横向NPN晶体管 （T1）。 PMOS晶体管（P1）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。
-
9.发明授权Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS circuits 失效双极SCR触发用于高速双极/ BiCMOS电路的ESD保护
公开(公告)号：US5808342A
公开(公告)日：1998-09-15
申请号：US721067
申请日：1996-09-26
CPC分类号： H01L27/0262
摘要： The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the NPN transistor. The turn-on voltage of the Zener is selected so as to be comparable to the emitter-base breakdown voltage of the NPN structure, which is only slightly higher than the power supply voltage to ensure that the ESD protection circuit will not be triggered under normal circuit operation. A forward diode string can optionally be added in series with the Zener to increase circuit trigger voltage, particularly in instances where the power supply voltage exceeds the Zener breakdown voltage. During an ESD event, when pad voltage exceeds Zener breakdown voltage, the Zener breaks down, and current flows through an associated (polysilicon) resistor to trigger the NPN of the Bipolar SCR and thus activate the BSCR to conduct the High ESD current from the associated, protected circuit.
摘要翻译： 本发明提供了双极结构，例如可控硅整流器（SCR），其显示有利地用于双极/ BiCMOS电路的高速（例如，900MHz-> 2GHz）亚微米ESD保护电路的低触发和保持电压。 双极结构在输入和输出引脚上具有低分流电容和低串联电阻，允许构建具有小的硅面积和信号路径中几乎没有阻抗的ESD保护电路。 在本发明的优选方面，如现有技术中常规的那样，将SCR组装在双极/ BiCMOS器件的N阱中，与P衬底相反。 本发明的优选方面利用齐纳二极管与电阻器组合来控制通过NPN晶体管的BSCR操作。 选择齐纳二极管的导通电压，以便与NPN结构的发射极 - 基极击穿电压相当，NPN结构的发射极击穿电压仅略高于电源电压，以确保ESD保护电路不会在正常情况下触发 电路操作。 特别是在电源电压超过齐纳击穿电压的情况下，正向二极管串可选择性地与齐纳二极管串联增加电路触发电压。 在ESD事件期间，当焊盘电压超过齐纳击穿电压时，齐纳二极管分解，电流流过相关（多晶硅）电阻器，以触发双极SCR的NPN，从而激活BSCR以从相关的 ，保护电路。
-
10.发明授权System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing 有权使用横向PNP或PMOS或两者用于衬底偏置的静电放电保护的系统和方法公开(公告)号：US06873506B2
公开(公告)日：2005-03-29
申请号：US10655865
申请日：2003-09-05
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H02H9/00
CPC分类号： H01L27/027 , H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1). Alternatively, the protective circuit (40) also may use a PMOS transistor (P1), or a PMOS transistor (P1) in combination with the lateral NPN transistor (T1), coupled to the input element (20) and to the lateral NPN transistor (T1). The PMOS transistor (P1) is operable to aid in raising the potential of the base of the lateral NPN transistor (T1).
摘要翻译： 本发明包括提供静电放电保护的系统和方法。 在本发明的一个实施例中，包括至少一个输入元件（20）的集成电路（10）由保护电路（40）保护。 保护电路（40）可操作以保护集成电路（10）免受静电放电所造成的损坏，并可与输入元件（20）耦合。 保护电路（40）包括耦合到输入元件（20）的横向NPN晶体管（T1），并且可操作以在输入元件电压超过阈值时启动，阈值大于或等于耦合到该电路的电路的正常工作电压 输入元件（20）。 保护电路（40）还可以包括耦合到输入元件（20）和横向NPN晶体管（T1）的横向PNP晶体管（T2）。 横向PNP晶体管（T2）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。 或者，保护电路（40）还可以使用PMOS晶体管（P1）或与横向NPN晶体管（T1）组合的PMOS晶体管（P1），耦合到输入元件（20）和横向NPN晶体管 （T1）。 PMOS晶体管（P1）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.019 秒)