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1.发明授权公开(公告)号：US09231201B2
公开(公告)日：2016-01-05
申请号：US11631212
申请日：2005-06-28
申请人： Robertus Theodorus Fransiscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
发明人： Robertus Theodorus Fransiscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
IPC分类号： H01L47/00 , H01L45/00 , B82Y10/00 , G11C13/02 , H01L21/285 , H01L21/768 , H01L27/24 , G11C13/00
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译： 根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。 记忆材料可以是相变材料。 电气设备（100）还包括电连接电子设备的第一端子（172）和存储器材料层（107）的一组纳米线（NW），从而能够经由纳米线传导来自第一端子的电流 （NW）和存储器材料层（107）连接到电气设备的第二端子（272）。 每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。 所有接触区域基本相同。 根据本发明的方法适用于制造根据本发明的电子设备（100）。
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公开(公告)号：US20080203463A1
公开(公告)日：2008-08-28
申请号：US11629800
申请日：2005-06-03
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/7883 , H01L29/42328
摘要： The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).
摘要翻译： 本发明提供一种非易失性存储器件及其制造方法。 该装置包括浮动栅极（16），控制栅极（19）和单独的擦除栅极（10）。 擦除栅极（10）设置在设置在基板（1）中的隔离区（2）中或隔离区（2）中。 因此，擦除门（10）不增加单元大小。 擦除栅极（10）和浮动栅极（16）之间的电容与控制栅极（19）和浮动栅极（16）之间的电容相比较小，并且充电的浮置栅极（16）被Fowler- Nordheim穿过擦除栅极（10）和浮动栅极（16）之间的氧化物层。
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公开(公告)号：US07419875B2
公开(公告)日：2008-09-02
申请号：US10537518
申请日：2003-10-31
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).
摘要翻译： 本发明提供一种在具有表面（2）的基板上制造浮栅型半导体器件的方法和由此制造的器件。 该方法包括：在衬底表面上形成包括绝缘膜（4），第一浮动浮栅材料层（6）和牺牲材料层（8）的叠层， - 形成至少一个隔离区（ 18）通过堆叠并进入衬底（2）中，第一层浮栅材料（6）由此具有顶表面和侧壁（26）， - 去除牺牲材料（8），从而留下空腔（20） ），并且用第二层浮栅材料（22）填充空腔（20），所述第一浮动栅极层（22）由所述隔离区（18）和所述第一浮栅材料层（6）的顶表面限定， 材料（6）和第二层浮栅材料（22），从而形成浮栅（24）。
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公开(公告)号：US07045852B2
公开(公告)日：2006-05-16
申请号：US10513874
申请日：2003-04-11
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L29/42324
摘要： A method to improve the coupling ratio between a control gate (18) and a floating gate (14) of a floating gate non-volatile semiconductor device is described. In a stacked gate floating gate transistor according to the invention, a conductive spacer (24) is used at both sides of the stack. The conductive spacer (24) is galvanically connected to the control gate (18), preferably by means of a conductive layer (34), whereas it is separated from the floating gate (14) by means of an insulating layer (22). The capacitance (C1, C2) between both conductive spacers (24) and the side walls of the floating gate (14) adds up to the normal capacitance between control gate (18) and floating gate (14).
摘要翻译： 描述了一种改善浮动栅极非易失性半导体器件的控制栅极（18）和浮动栅极（14）之间的耦合比的方法。 在根据本发明的堆叠栅极浮栅晶体管中，在堆叠的两侧使用导电间隔物（24）。 导电间隔物（24）优选通过导电层（34）电连接到控制栅极（18），而通过绝缘层（22）与导电间隔物（24）分离。 两个导电间隔物（24）和浮动栅极（14）的侧壁之间的电容（C 1，C 2）与控制栅极（18）和浮动栅极（14）之间的正常电容相加。
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公开(公告)号：US07709879B2
公开(公告)日：2010-05-04
申请号：US11629800
申请日：2005-06-03
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L29/42328
摘要： The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).
摘要翻译： 本发明提供一种非易失性存储器件及其制造方法。 该装置包括浮动栅极（16），控制栅极（19）和单独的擦除栅极（10）。 擦除栅极（10）设置在设置在基板（1）中的隔离区（2）中或隔离区（2）中。 因此，擦除门（10）不增加单元大小。 擦除栅极（10）和浮动栅极（16）之间的电容与控制栅极（19）和浮动栅极（16）之间的电容相比较小，并且充电的浮置栅极（16）被Fowler- Nordheim穿过擦除栅极（10）和浮动栅极（16）之间的氧化物层。
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公开(公告)号：US20080303076A1
公开(公告)日：2008-12-11
申请号：US12175521
申请日：2008-07-18
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).
摘要翻译： 本发明提供一种在具有表面（2）的基板上制造浮栅型半导体器件的方法和由此制造的器件。 该方法包括：在衬底表面上形成包括绝缘膜（4），第一浮动浮栅材料层（6）和牺牲材料层（8）的叠层， - 形成至少一个隔离区（ 18）通过堆叠并进入衬底（2）中，第一层浮栅材料（6）由此具有顶表面和侧壁（26）， - 去除牺牲材料（8），从而留下空腔（20） ），并且用第二层浮栅材料（22）填充空腔（20），所述第一浮动栅极层（22）由所述隔离区（18）和所述第一浮栅材料层（6）的顶表面限定， 材料（6）和第二层浮栅材料（22），从而形成浮栅（24）。
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7.发明申请Non-Volatile Memory Device Having a Gap in the Tunnuel Insulating Layer and Method of Manufacturing the Same 审中-公开在隧道绝缘层中具有间隙的非易失性存储器件及其制造方法公开(公告)号：US20080265306A1
公开(公告)日：2008-10-30
申请号：US12097144
申请日：2006-12-11
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7883 , H01L29/792
摘要： A non-volatile memory device (1, 101, 201, 301) having a gap within a tunnel dielectric layer (14, 114, 214, 314) and a method of manufacturing the same is provided. The devices have a stack of layers on top of a substrate (10, 110, 210, 310) including, a charge tunneling layer with a gap (14, 114, 214, 314), a charge storage layer (16, 116, 216, 316), a control gate layer (20, 120, 220, 320) and an insulating layer (18, 118, 218 220) in between the charge storage layer and the control gate. Manufacturing proceeds through deposition of a sacrificial layer (28, 128,228,328) on parts of a substrate, whereupon a stack of layers (24, 124,224,324) including a charge-storage layer, an insulating layer and a control gate layer are formed. Subsequently, selected parts of the sacrificial layer are removed, thereby forming a gap in between the charge storage region and the substrate. The gap is protected from future processing by deposition of a sealing layer (34, 134, 234, 334). Such a device has a reduced operating voltage and its manufacture can be easily implemented in existing semiconductor processes.
摘要翻译： 提供了在隧道介电层（14,114,214,314）内具有间隙的非易失性存储器件（1,101,201,301）及其制造方法。 这些器件在衬底（10,110,210,310）的顶部上具有一叠层，包括具有间隙（14,114,214,314）的电荷隧道层，电荷存储层（16,116,216） ，316），在电荷存储层和控制栅之间的控制栅极层（20,120,220,320）和绝缘层（18,118,218220）。 通过在衬底的部分上沉积牺牲层（28,128,228,328）来进行制造，由此形成包括电荷存储层，绝缘层和控制栅极层的层叠层（24,124,224,324）。 随后，去除牺牲层的选定部分，从而在电荷存储区域和基板之间形成间隙。 通过沉积密封层（34,134,234,334）来保护间隙免于将来的加工。 这种器件具有降低的工作电压，并且其制造可以容易地在现有的半导体工艺中实现。
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公开(公告)号：US07763512B2
公开(公告)日：2010-07-27
申请号：US12175521
申请日：2008-07-18
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).
摘要翻译： 本发明提供一种在具有表面（2）的基板上制造浮栅型半导体器件的方法和由此制造的器件。 该方法包括：在衬底表面上形成包括绝缘膜（4），第一浮动浮栅材料层（6）和牺牲材料层（8）的叠层， - 形成至少一个隔离区（ 18）通过堆叠并进入衬底（2）中，第一层浮栅材料（6）由此具有顶表面和侧壁（26）， - 去除牺牲材料（8），从而留下空腔（20） ），并且用第二层浮栅材料（22）填充空腔（20），所述第一浮动栅极层（22）由所述隔离区（18）和所述第一浮栅材料层（6）的顶表面限定， 材料（6）和第二层浮栅材料（22），从而形成浮栅（24）。
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公开(公告)号：US07429513B2
公开(公告)日：2008-09-30
申请号：US10546748
申请日：2004-02-13
申请人： Michiel Jos Van Duuren , Robertus Theodorus Fransiscus Van Schaijk , Youri Ponomarev , Jacob Christopher Hooker
发明人： Michiel Jos Van Duuren , Robertus Theodorus Fransiscus Van Schaijk , Youri Ponomarev , Jacob Christopher Hooker
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328 , H01L29/66825
摘要： In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9). A second sacrificial layer (20) is used to protect the part (82) off the surface (2) adjacent to the second sidewall (81) and opposite to the position (83) of the second stack (7) when providing the access gate layer (14).
摘要翻译： 在制造半导体器件（100）的方法中，其包括具有源极区（3）的表面（2）和限定沟道方向（102）的漏极区（4）的半导体（1）和通道 区域（101），在沟道区域（101）的顶部上的第一层叠层（6），第一堆叠（6）依次包括隧道介电层（11），电荷存储层（10） 用于在通道方向（102）上直接与第一堆叠（6）相邻的通道区域（101）的顶部上存储电荷和控制栅极层（9）以及第二堆叠（7）， 第二堆叠（7）包括与半导电体（1）和第一堆叠（6）电绝缘的存取栅极层（14），最初使用第一牺牲层（90），其随后由控制栅极 层（9）。 当提供接入门（20）时，第二牺牲层（20）用于保护邻近第二侧壁（81）的表面（2）并且与第二堆叠（7）的位置（83）相对的部分（82） 层（14）。
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公开(公告)号：US08794054B2
公开(公告)日：2014-08-05
申请号：US13262628
申请日：2010-03-25
IPC分类号： G01N29/036
CPC分类号： G01N33/5438 , B81C1/00087 , G01N33/48721
摘要： A sensor device for analyzing fluidic samples is provided. The sensor device includes a stacked sensing arrangement having at least three sensing layers and a multilayer structure. The multilayer structure has a hole formed therein which is adapted to let pass the fluidic sample and the stacked sensing arrangement is formed in the multilayer structure in such a way that the fluidic sample passes the stacked sensing arrangement when the fluidic sample passes the hole.
摘要翻译： 提供了一种用于分析流体样品的传感器装置。 传感器装置包括具有至少三个感测层和多层结构的层叠感测装置。 多层结构具有形成在其中的孔，其适于使流体样品通过，并且层叠的感测装置形成在多层结构中，使得当流体样品通过孔时流体样品通过堆叠的感测装置。
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