公开(公告)号：US11691872B2

公开(公告)日：2023-07-04

申请号：US17713410

申请日：2022-04-05

申请人： Applied Materials, Inc.

发明人： Philip Allan Kraus ,  Joseph R. Johnson

IPC分类号： B81C1/00 ,  H01L21/02 ,  G01N33/487 ,  G01N27/49 ,  H01L21/302

CPC分类号： B81C1/00087 ,  G01N27/49 ,  G01N33/48721 ,  H01L21/0228 ,  H01L21/302

摘要： Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays thereof. In one aspect, methods for manufacturing nanopores and arrays thereof exploit a physical seam. One or more etch pits are formed in a topside of a substrate and one or more trenches, which align with the one or more etch pits, are formed in a backside of the substrate. An opening is formed between the one or more etch pits and the one or more trenches. A dielectric material is then formed over the substrate to fill the opening. Contacts are then disposed on the topside and the backside of the substrate and a voltage is applied from the topside to the backside, or vice versa, through the dielectric material to form a nanopore. In another aspect, the nanopore is formed at or near the center of the opening at a seam, which is formed in the dielectric material.

公开(公告)号：US20190233280A1

公开(公告)日：2019-08-01

申请号：US16213019

申请日：2018-12-07

申请人： Shenyang Silicon Technology Co., Ltd.

发明人： Xiang LI

IPC分类号： B81C1/00 ,  B81B1/00

CPC分类号： B81C1/00047 ,  B08B3/08 ,  B32B37/06 ,  B32B38/0008 ,  B32B43/006 ,  B32B2038/0016 ,  B32B2310/14 ,  B32B2313/00 ,  B32B2457/14 ,  B81B1/004 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00357 ,  B81C1/00507 ,  B81C1/00849 ,  B81C2201/0116 ,  B81C2201/0125 ,  B81C2201/0178 ,  B81C2201/019 ,  B81C2201/0192 ,  B81C2201/0194

摘要： A method for processing a silicon wafer with a through cavity structure. The method is operated in accordance with the following sequence: performing ion implantation on a silicon wafer or pattern wafer; implanting a dummy substrate; bonding the silicon wafer to the pattern wafer; performing grinding and polishing, and thinning the pattern wafer to a depth exposing the pattern; bonding; and peeling the dummy substrate. Compared with the prior art, the present invention is standard in operation, and the product quality can be effectively guaranteed. The product has high cost performance and excellent comprehensive technical effect. The present invention has expectable relatively large economic values and social values.

公开(公告)号：US20190004030A1

公开(公告)日：2019-01-03

申请号：US16063982

申请日：2016-03-18

申请人： Hitachi, Ltd.

发明人： Itaru YANAGI ,  Kenichi TAKEDA

IPC分类号： G01N33/487 ,  B81C1/00

CPC分类号： G01N33/48721 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00158 ,  C12Q1/6869 ,  C12Q2565/631

摘要： A method of manufacturing a membrane device comprises: a first step of forming a pillar structure on a part of a Si substrate by etching; a second step of forming a first insulation layer on the Si substrate so as to expose a Si surface of an upper part of the pillar structure; a third step of forming a second insulation layer on the pillar structure and the first insulation layer; and a fourth step of etching the Si substrate from an opposite side of the second insulation layer and etching the pillar structure with the first insulation layer being a mask, to thereby form a membrane, which is a region free of the pillar structure in the second insulation layer.

公开(公告)号：US20180147848A1

公开(公告)日：2018-05-31

申请号：US15817963

申请日：2017-11-20

申请人： CANON KABUSHIKI KAISHA

发明人： Atsushi Teranishi ,  Masaya Uyama

IPC分类号： B41J2/16 ,  B81B1/00 ,  B81C1/00

CPC分类号： B41J2/16 ,  B41J2/14145 ,  B41J2/1603 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1642 ,  B41J2/1645 ,  B41J2/1646 ,  B41J2002/14467 ,  B81B1/004 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C2201/019 ,  B81C2203/032

摘要： A method for forming a film that covers a side wall of a through hole in a substrate having the through hole, the method including, in the following order, the steps of providing a substrate having a through hole that passes therethrough from a first surface to a second surface, which is a surface opposite to the first surface, forming, on the first surface, a lid member that blocks an opening of the through hole open on the first surface, recessing, in a direction away from the first surface, a surface of the lid member that blocks the opening by removing part of the lid member through the opening, and forming a film that covers the side wall of the through hole.

公开(公告)号：US09975761B2

公开(公告)日：2018-05-22

申请号：US15444086

申请日：2017-02-27

申请人： SMARTTIP BV

发明人： Edin Sarajlic

IPC分类号： B81C1/00 ,  A61B5/15

CPC分类号： B81C1/0015 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150396 ,  A61B5/150511 ,  A61B5/150519 ,  A61B5/150984 ,  A61B5/15142 ,  A61M37/0015 ,  B81B2201/057 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00111 ,  B81C1/00119 ,  B81C2201/0132 ,  B81C2201/0143 ,  B81C2201/0159 ,  B81C2201/0198 ,  C01B21/0687

摘要： A method of manufacturing a plurality of through-holes in a layer of first material, for example for the manufacturing of a probe comprising a tip containing a channel. To manufacture the through-holes in a batch process, a layer of first material is deposited on a wafer comprising a plurality of pits a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits; using the second layer as a shadow mask when depositing a third layer at an angle, covering a part of the first material with said third material at the central locations, and etching the exposed parts of the first layer using the third layer as a protective layer.

公开(公告)号：US20180130728A1

公开(公告)日：2018-05-10

申请号：US15791152

申请日：2017-10-23

申请人： SEIKO EPSON CORPORATION

发明人： Kazuhiro GOMI

IPC分类号： H01L23/498 ,  H01L21/768 ,  B41J2/16 ,  B81C1/00 ,  H01L21/268 ,  H01L21/306

CPC分类号： H01L23/49827 ,  B41J2/161 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1634 ,  B41J2/1645 ,  B81C1/00087 ,  B81C2201/0143 ,  H01L21/268 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon substrate processing method includes forming an etching mask which has an opening portion, on a surface of a silicon substrate, forming an etching guide hole in the opening portion on the silicon substrate, and forming a through-hole which passes through the silicon substrate, by applying an etching treatment onto the silicon substrate in which the etching guide hole is formed. In the forming of the guide hole, the etching guide hole passing through the silicon substrate is formed by irradiating the opening portion with a laser beam a plurality of times, with a cooling period between each instance of irradiation with the laser beam.

公开(公告)号：US09914118B2

公开(公告)日：2018-03-13

申请号：US14824518

申请日：2015-08-12

申请人： International Business Machines Corporation

发明人： Yann A. Astier ,  Markus Brink ,  Michael F. Lofaro ,  Joshua T. Smith

IPC分类号： G01N27/447 ,  B01L3/00 ,  G01N33/487 ,  B81C1/00 ,  B24B37/04 ,  G01N30/74 ,  G01N30/60 ,  G01N30/88

CPC分类号： B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L2200/0652 ,  B01L2200/12 ,  B01L2300/0681 ,  B01L2300/0858 ,  B01L2300/0887 ,  B01L2300/0896 ,  B24B37/042 ,  B81C1/00087 ,  B81C2201/0104 ,  B81C2201/013 ,  G01N27/44791 ,  G01N30/6039 ,  G01N30/74 ,  G01N33/48721 ,  G01N2030/885

摘要： A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

公开(公告)号：US09782773B2

公开(公告)日：2017-10-10

申请号：US14950320

申请日：2015-11-24

申请人： International Business Machines Corporation

发明人： Yann A. Astier ,  Markus Brink ,  Michael F. Lofaro ,  Joshua T. Smith

IPC分类号： H01L21/311 ,  B01L3/00 ,  B81C1/00 ,  B24B37/04 ,  G01N27/447 ,  G01N33/487 ,  G01N30/74 ,  G01N30/60 ,  G01N30/88

CPC分类号： B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L2200/0652 ,  B01L2200/12 ,  B01L2300/0681 ,  B01L2300/0858 ,  B01L2300/0887 ,  B01L2300/0896 ,  B24B37/042 ,  B81C1/00087 ,  B81C2201/0104 ,  B81C2201/013 ,  G01N27/44791 ,  G01N30/6039 ,  G01N30/74 ,  G01N33/48721 ,  G01N2030/885

摘要： A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

公开(公告)号：US09777389B2

公开(公告)日：2017-10-03

申请号：US14399071

申请日：2013-05-07

申请人： THE UNIVERSITY OF OTTAWA

发明人： Wing Hei Kwok ,  Vincent Tabard-Cossa ,  Kyle Alexander Zarkel Briggs

IPC分类号： C25F3/14 ,  B01D67/00 ,  B01D65/02 ,  G01N33/487 ,  C25F7/00 ,  G01B7/00 ,  G01N27/04 ,  G01N33/00 ,  B81C1/00 ,  B82Y15/00

CPC分类号： C25F3/14 ,  B01D65/02 ,  B01D67/009 ,  B01D2321/22 ,  B01D2323/42 ,  B01D2325/02 ,  B81B2203/0353 ,  B81C1/00087 ,  B82Y15/00 ,  C25F7/00 ,  G01B7/00 ,  G01N27/04 ,  G01N33/00 ,  G01N33/48721 ,  G01N2033/0095

摘要： A method is provided for fabricating a nanopore in a membrane. The method includes: applying an electric potential across the membrane, where value of the electric potential is selected to induce an electric field which causes a leakage current across the membrane; monitoring current flow across the membrane while the electric potential is being applied; detecting an abrupt increase in the leakage current across the membrane; and removing the electric potential across the membrane in response to detecting the abrupt increase in the leakage current.

公开(公告)号：US20170129767A1

公开(公告)日：2017-05-11

申请号：US15411957

申请日：2017-01-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

发明人： Tsai-Hao HUNG ,  Shih-Chi KUO ,  Tsung-Hsien LEE ,  Tao-Cheng LIU

IPC分类号： B81B1/00 ,  B81C1/00

CPC分类号： B81B1/004 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0163 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/012 ,  B81C1/00087 ,  B81C1/00619 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2203/0118

摘要： The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.