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17 条记录 (耗时 0.032 秒)

    Semiconductor wafer process chamber with suspector back coating
    3.
    发明授权
    Semiconductor wafer process chamber with suspector back coating 失效
    半导体晶圆处理室具有悬挂背面涂层

    公开(公告)号：US5599397A

    公开(公告)日：1997-02-04

    申请号：US625271

    申请日：1996-03-27

    申请人： Roger N. Anderson ,  H. Peter W. Hey ,  Israel Beinglass ,  Mahalingam Venkatesan

    发明人： Roger N. Anderson ,  H. Peter W. Hey ,  Israel Beinglass ,  Mahalingam Venkatesan

    IPC分类号： C30B25/08 ,  C23C14/50 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C30B25/10 ,  C30B25/14 ,  H01L21/205 ,  H01L21/31 ,  C23C16/00

    CPC分类号： C23C16/45502 ,  C23C16/455 ,  C23C16/45561 ,  C23C16/45563 ,  C23C16/4581 ,  C30B25/105 ,  C30B25/14

    摘要： The present disclosure is directed to an apparatus for depositing a layer of a material on a wafer. The apparatus includes a deposition chamber having an upper dome, a lower dome and a side wall between the upper and lower domes. A susceptor plate is in and extends across the deposition chamber to divide the deposition chamber into an upper portion above the susceptor plate and a lower portion below the susceptor plate. A gas inlet manifold is in the side wall. The manifold has three inlet ports. One of the ports is connected by passages which open into the lower portion of the deposition chamber. The other two ports are connected by passages which open into the upper portion of the deposition chamber. A gas supply system is connected to the inlet ports so as to provide the same gases into the lower portion of the deposition chamber as well as into the upper portion of the deposition chamber. This allows the back surface of the susceptor plate to be coated with a layer of the same material as to be coated on the wafer prior to coating the layer on the wafer.

    摘要翻译： 本公开涉及一种用于在晶片上沉积材料层的装置。 该装置包括具有上圆顶，下圆顶和在上下圆顶之间的侧壁的沉积室。 感受板在沉积室中并且延伸穿过沉积室，以将沉积室分成基座板上方的上部和基座板下方的下部。 气体入口歧管位于侧壁中。 歧管有三个入口。 一个端口通过通向沉积室的下部的通道连接。 其他两个端口通过通向沉积室的上部的通道连接。 气体供给系统连接到入口端口，以便将相同的气体提供到沉积室的下部以及沉积室的上部。 这允许在将晶片上的层涂覆之前，使基座板的背面涂覆有要涂覆在晶片上的相同材料的层。

    Semiconductor wafer process chamber with susceptor back coating
    4.
    发明授权
    Semiconductor wafer process chamber with susceptor back coating 失效
    半导体晶圆处理室，带底座背面涂层

    公开(公告)号：US5551982A

    公开(公告)日：1996-09-03

    申请号：US221118

    申请日：1994-03-31

    申请人： Roger N. Anderson ,  H. Peter W. Hey ,  Israel Beinglass ,  Mahalingam Venkatesan

    发明人： Roger N. Anderson ,  H. Peter W. Hey ,  Israel Beinglass ,  Mahalingam Venkatesan

    IPC分类号： C30B25/08 ,  C23C14/50 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C30B25/10 ,  C30B25/14 ,  H01L21/205 ,  H01L21/31 ,  C23C16/00

    CPC分类号： C23C16/45502 ,  C23C16/455 ,  C23C16/45561 ,  C23C16/45563 ,  C23C16/4581 ,  C30B25/105 ,  C30B25/14

    摘要： The present disclosure is directed to an apparatus for depositing a layer of a material on a wafer. The apparatus includes a deposition chamber having an upper dome, a lower dome and a side wall between the upper and lower domes. A susceptor plate is in and extends across the deposition chamber to divide the deposition chamber into an upper portion above the susceptor plate and a lower portion below the susceptor plate. A gas inlet manifold is in the side wall. The manifold has three inlet ports. One of the ports is connected by passages which open into the lower portion of the deposition chamber. The other two ports are connected by passages which open into the upper portion of the deposition chamber. A gas supply system is connected to the inlet ports so as to provide the same gases into the lower portion of the deposition chamber as well as into the upper portion of the deposition chamber. This allows the back surface of the susceptor plate to be coated with a layer of the same material as to be coated on the wafer prior to coating the layer on the wafer.

    摘要翻译： 本公开涉及一种用于在晶片上沉积材料层的装置。 该装置包括具有上圆顶，下圆顶和在上下圆顶之间的侧壁的沉积室。 感受板在沉积室中并且延伸穿过沉积室，以将沉积室分成基座板上方的上部和基座板下方的下部。 气体入口歧管位于侧壁中。 歧管有三个入口。 一个端口通过通向沉积室的下部的通道连接。 其他两个端口通过通向沉积室的上部的通道连接。 气体供给系统连接到入口端口，以便将相同的气体提供到沉积室的下部以及沉积室的上部。 这允许在将晶片上的层涂覆之前，使基座板的背面涂覆有要涂覆在晶片上的相同材料的层。

    Low temperature etching in cold-wall CVD systems
    5.
    发明授权
    Low temperature etching in cold-wall CVD systems 失效
    冷壁CVD系统中的低温蚀刻

    公开(公告)号：US5421957A

    公开(公告)日：1995-06-06

    申请号：US100582

    申请日：1993-07-30

    申请人： David K. Carlson ,  H. Peter W. Hey ,  James C. Hann

    发明人： David K. Carlson ,  H. Peter W. Hey ,  James C. Hann

    IPC分类号： H01L21/205 ,  C23C16/44 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  B44C1/22

    CPC分类号： C23C16/4405

    摘要： An improved method of etching or cleaning a cold-wall chemical vapor deposition chamber that is substantially moisture-free at a low chamber temperature and a low chamber pressure while maintaining a satisfactory etch rate by using at least one etchant gas selected from the group consisting of nitrogen trifluoride, chlorine trifluoride, sulfur hexafluoride, carbon tetrafluoride or the like and mixtures thereof.

    摘要翻译： 一种蚀刻或清洁冷壁化学气相沉积室的改进方法，其在低室温度和低室压力下基本上不含湿气，同时通过使用至少一种蚀刻剂气体来保持令人满意的蚀刻速率，所述蚀刻剂气体选自 三氟化氮，三氟化氯，六氟化硫，四氟化碳等，以及它们的混合物。

    Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
    6.
    发明授权
    Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics 有权
    使用具有不同蚀刻特性的电介质层由双镶嵌线形成的互连线

    公开(公告)号：US06514671B1

    公开(公告)日：2003-02-04

    申请号：US09675989

    申请日：2000-09-29

    申请人： Suketu A. Parikh ,  Mehul B. Naik ,  Samuel Broydo ,  H. Peter W. Hey

    发明人： Suketu A. Parikh ,  Mehul B. Naik ,  Samuel Broydo ,  H. Peter W. Hey

    IPC分类号： G03C500

    CPC分类号： H01L21/76808 ,  H01L23/485 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).

    摘要翻译： 本发明提供集成电路制造方法和装置，其中双镶嵌结构（332和334）形成在具有不同蚀刻特性的连续介电层（314和316）中。 本发明还提供了这样的方法和装置，其中这些介电层具有不同的介电常数。 本发明的另外的实施方案包括使用单层掩模，例如在暴露于辐射时形成硬掩模（622）的硅基感光材料。 在另外的实施例中，制造系统（710）用于制造IC结构。 这些系统包括适于与多个制造站（720,722,724,726,728和730）相互作用的控制器（700）。

    Method and apparatus for improving film deposition uniformity on a substrate
    7.
    发明授权
    Method and apparatus for improving film deposition uniformity on a substrate 失效
    提高基板上成膜均匀性的方法和装置

    公开(公告)号：US6022587A

    公开(公告)日：2000-02-08

    申请号：US855247

    申请日：1997-05-13

    申请人： H. Peter W. Hey ,  Vedapuram S. Achutharaman ,  Johanes F. N. Swenberg

    发明人： H. Peter W. Hey ,  Vedapuram S. Achutharaman ,  Johanes F. N. Swenberg

    IPC分类号： C23C16/44 ,  H01L21/205 ,  H01L21/285 ,  C23C16/42

    CPC分类号： C23C16/44 ,  C23C16/4404

    摘要： A method and apparatus for depositing a film on a substrate. According to the present invention a prewafer reaction layer is deposited onto a susceptor placed in the reaction chamber to form a prewafer reaction layer coated susceptor prior to film deposition. A deposition gas is then fed into the reaction chamber so that it flows over the prewafer reaction layer coated susceptor and the substrate to form a film on the prewafer reaction layer coated susceptor and the substrate.

    摘要翻译： 一种用于在基板上沉积膜的方法和装置。 根据本发明，预沉积反应层沉积在放置在反应室中的基座上，以便在膜沉积之前形成预先覆盖的反应层涂覆的基座。 然后将沉积气体进料到反应室中，使其流过预先预处理的反应层涂覆的基座和基底，以在预先涂覆的反应层涂覆的基座和基底上形成膜。