公开(公告)号：US5689516A

公开(公告)日：1997-11-18

申请号：US670916

申请日：1996-06-26

申请人： Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

发明人： Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G06F11/00

CPC分类号： G01R31/318516 ,  G01R31/318558 ,  G06F11/2215

摘要： A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

摘要翻译： 可编程逻辑器件（PLD）包括与JTAG标准（IEEE标准1149.1）兼容的测试电路。 PLD还包括一个可编程JTAG禁止位，可以选择性地编程禁止JTAG电路，使PLD能够作为传统的非JTAG兼容PLD运行。 PLD还包括用于测试JTAG测试电路以确定JTAG电路是否有故障的装置，以及如果测试装置确定JTAG电路有故障，则用于编程JTAG禁用位以禁用JTAG电路的装置。

公开(公告)号：US5661685A

公开(公告)日：1997-08-26

申请号：US533131

申请日：1995-09-25

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

IPC分类号： G11C16/02 ,  G06F17/50 ,  H03K19/177 ,  G11C7/00

CPC分类号： H03K19/17784 ,  G06F17/5054 ,  H03K19/17704

摘要： An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

摘要翻译： 集成可编程逻辑器件（PLD）包括闪存EPROM存储晶体管。 PLD包括多路复用器，其选择性地向存储晶体管提供编程，擦除或验证电压。 可以使用外部电源提供程序，擦除和验证电压，或者可以由片上电荷泵发生器内部产生。 PLD上的可配置存储器用于调整每个片上电荷泵发生器的输出电压。

公开(公告)号：US06175246B1

公开(公告)日：2001-01-16

申请号：US09577193

申请日：2000-05-23

申请人： Mihai G. Statovici ,  Ronald J. Mack

发明人： Mihai G. Statovici ,  Ronald J. Mack

IPC分类号： G01R3126

CPC分类号： G01R31/3191

摘要： A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

摘要翻译： 提供了一种提高AC参数测试精度的方法和系统。 本发明提供一种在集成电路测试装置中精确估计信号传播延迟时间的方法，其中采用多个信号传播延迟时间测量，并通过线性内插所测量的延迟来估计额外的延迟时间。 建立所需的测试点（给定时间的期望输出电压）。 使用样品装置，通过所需的测试点，在一段时间与电压曲线上建立斜率。 如果所需的测试点在测试仪的选通时间之间，则使用线性外推来计算在两个包围选通时间必须测试的电压，以保证在期望的测试点所需的性能。 然后在相应的包围选通时间测试一个或多个器件的计算电压。

公开(公告)号：US6124724A

公开(公告)日：2000-09-26

申请号：US85983

申请日：1998-05-27

申请人： Mihai G. Statovici ,  Ronald J. Mack

发明人： Mihai G. Statovici ,  Ronald J. Mack

IPC分类号： G01R31/319 ,  G01R31/26

CPC分类号： G01R31/3191

摘要： A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

摘要翻译： 提供了一种提高AC参数测试精度的方法和系统。 本发明提供一种在集成电路测试装置中精确估计信号传播延迟时间的方法，其中采用多个信号传播延迟时间测量，并通过线性内插所测量的延迟来估计额外的延迟时间。 建立所需的测试点（给定时间的期望输出电压）。 使用样品装置，通过所需的测试点，在一段时间与电压曲线上建立斜率。 如果所需的测试点落在测试仪的选通时间之间，则使用线性外推来计算在两个包围选通时间必须测试的电压，以保证在期望的测试点所需的性能。 然后在相应的包围选通时间测试一个或多个器件的计算电压。

公开(公告)号：US06552526B1

公开(公告)日：2003-04-22

申请号：US09578793

申请日：2000-05-23

申请人： Mihai G. Statovici ,  Ronald J. Mack

发明人： Mihai G. Statovici ,  Ronald J. Mack

IPC分类号： G01R1900

CPC分类号： G01R31/3191

摘要： A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

摘要翻译： 提供了一种提高AC参数测试精度的方法和系统。 本发明提供一种在集成电路测试装置中精确估计信号传播延迟时间的方法，其中采用多个信号传播延迟时间测量，并通过线性内插所测量的延迟来估计额外的延迟时间。 建立所需的测试点（给定时间的期望输出电压）。 使用样品装置，通过所需的测试点，在一段时间与电压曲线上建立斜率。 如果所需的测试点落在测试仪的选通时间之间，则使用线性外推来计算在两个包围选通时间必须测试的电压，以保证在期望的测试点所需的性能。 然后在相应的包围选通时间测试一个或多个设备的计算电压。

公开(公告)号：US06367041B1

公开(公告)日：2002-04-02

申请号：US09670992

申请日：2000-09-26

申请人： Mihai G. Statovici ,  Ronald J. Mack

发明人： Mihai G. Statovici ,  Ronald J. Mack

IPC分类号： G01R3128

CPC分类号： G01R31/01

摘要： A method and software apparatus for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. A modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.

摘要翻译： 一种方法和软件设备，用于实现适应每个处理的设备批次的特性的用于集成电路设备的可动态修改的测试流程。 执行足够确保特定批次的适当装置功能的经过修改的一组测试，可降低测试成本并提高测试能力。 本发明的方法和系统使用包括一组可跳过测试的全套测试周期性地对预定的样本数量的设备进行采样。 根据可跳过测试中的样品器件组的性能特征，在修改的测试流程中会跳过多个可跳过的测试。 在使用修改的测试流程测试下一组设备后，再次对另一个样本组进行全套测试，并根据新结果调整修改的测试流程的大小和组成。

公开(公告)号：US6167545A

公开(公告)日：2000-12-26

申请号：US44585

申请日：1998-03-19

申请人： Mihai G. Statovici ,  Ronald J. Mack

发明人： Mihai G. Statovici ,  Ronald J. Mack

IPC分类号： G01R31/01 ,  G01R31/28

CPC分类号： G01R31/01

摘要： A method and software apparatus are provided for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. According to the method of the invention, a modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results. A test summary logs the results of regular and skippable tests, providing user access to enable system modification according to desired acceptance quality levels.

摘要翻译： 提供了一种方法和软件设备，用于为适应每个被处理设备批次的特性的集成电路设备实现可动态修改的测试流程。 根据本发明的方法，执行足够确保特定批次的适当装置功能的改进的一组测试，降低了测试成本并提高了测试能力。 本发明的方法和系统使用包括一组可跳过测试的全套测试周期性地对预定的样本数量的设备进行采样。 根据可跳过测试中的样品器件组的性能特征，在修改的测试流程中会跳过多个可跳过的测试。 在使用修改的测试流程测试下一组设备后，再次对另一个样本组进行全套测试，并根据新结果调整修改的测试流程的大小和组成。 测试摘要记录常规和可跳过测试的结果，提供用户访问以根据期望的接受质量水平启用系统修改。

公开(公告)号：US5923602A

公开(公告)日：1999-07-13

申请号：US44584

申请日：1998-03-19

申请人： Mihai G. Statovici ,  Ronald J. Mack

发明人： Mihai G. Statovici ,  Ronald J. Mack

IPC分类号： G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C16/04

摘要： A method is described for testing the programming function of integrated circuit device cells including floating gate elements. To accelerate the testing process, at most two programming pulses are needed, the two pulses being applied with the device at minimum and maximum power supply voltage levels specified for the device. First, the cell state after an initial programming pulse with the device at a minimum power supply voltage level, tested against a minimum reference voltage level, indicates whether the cell is programming properly. If not, testing ceases immediately and the device is rejected after the first pulse. Devices passing the first reading after the first pulse are subjected to a second reading at the target (higher) reference voltage. Devices passing after the second reading are designated as passing and are subjected to the next test in the test flow. Devices failing the second reading are subjected to a second programming pulse, applied with the device at the maximum power supply voltage level, the resulting cell state providing an indication of cell programming functionality. The same pulse series can also be used to test erase functionality.

摘要翻译： 描述了用于测试包括浮动栅极元件的集成电路器件单元的编程功能的方法。 为了加速测试过程，最多需要两个编程脉冲，两个脉冲以设备规定的最小和最大电源电压电平施加在器件上。 首先，在器件处于最小电源电压电平的初始编程脉冲之后的单元状态，针对最小参考电压电平进行测试，指示单元是否正确编程。 如果没有，测试将立即停止，设备在第一个脉冲后被拒绝。 在第一脉冲之后通过第一读取的器件在目标（较高）参考电压下进行第二读取。 在二读后通过的装置被指定为通过，并在试验流程中进行下一次试验。 二次读取失败的器件经受第二编程脉冲，以最大电源电压电平施加该器件，所得到的单元状态提供单元编程功能的指示。 同样的脉冲串也可以用来测试擦除功能。

公开(公告)号：US07496820B1

公开(公告)日：2009-02-24

申请号：US11369670

申请日：2006-03-07

申请人： Conrad A. Theron ,  Michael L. Simmons ,  Walter H. Edmondson ,  Mihai G. Statovici

发明人： Conrad A. Theron ,  Michael L. Simmons ,  Walter H. Edmondson ,  Mihai G. Statovici

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  G01R31/31813

摘要： Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

摘要翻译： 描述了用于产生被测集成电路（IC）的测试向量的方法，装置和计算机可读介质。 在一个示例中，使用至少一个基本功能来指定测试功能，该基本功能封装与被测IC的架构相关联的程序代码。 引擎配置有被测试IC的设备描述数据。 引擎以测试功能作为参数输入来执行，以生成测试向量。 在一个示例中，所测试的IC包括可编程逻辑器件（PLD），并且测试向量包括用于配置PLD中的模式的配置数据和用于执行模式的至少一个测试向量。 测试矢量可以直接应用于设备或通过自动测试设备（ATE）。 或者，测试向量可以应用于设备的IC设计仿真。

公开(公告)号：US5825787A

公开(公告)日：1998-10-20

申请号：US978163

申请日：1997-11-25

申请人： Mihai G. Statovici

发明人： Mihai G. Statovici

IPC分类号： G01R31/319 ,  G06F11/20 ,  G06F11/00

CPC分类号： G01R31/31921

摘要： An improved circuit tester allows for increased storage of test vectors in existing memory structures by noting where segments of test vectors repeat and storing such segments only once, then further utilizing memory space corresponding to otherwise unused test channels. Switching circuitry is included to selectively forward signals to and from a designated, multi-source conductor.

摘要翻译： 改进的电路测试器允许通过注意测试向量的区段重复并存储这些段仅一次，从而进一步利用对应于否则未使用的测试信道的存储器空间来增加现有存储器结构中测试向量的存储。 包括开关电路以选择性地将信号转发到指定的多源导体和从指定的多源导体转发信号。