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    Floating gate device with graphite floating gate
    1.
    发明授权
    Floating gate device with graphite floating gate 有权
    带石墨浮动门的浮闸装置

    公开(公告)号：US07978504B2

    公开(公告)日：2011-07-12

    申请号：US12131938

    申请日：2008-06-03

    Applicant: Ronald Kakoschke ,  Harald Seidl

    Inventor： Ronald Kakoschke ,  Harald Seidl

    IPC: G11C11/00

    CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4966

    Abstract: One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.

    Abstract translation: 一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述基板上的电荷存储层; 以及设置在所述电荷存储层上的控制栅极，其中所述电荷存储层或所述控制栅极层包含碳同素异形体。

    Memory device comprising select gate including carbon allotrope
    2.
    发明授权
    Memory device comprising select gate including carbon allotrope 有权
    存储器件包括选择栅极，包括碳同素异形体

    公开(公告)号：US08199560B2

    公开(公告)日：2012-06-12

    申请号：US13156370

    申请日：2011-06-09

    Applicant: Ronald Kakoschke ,  Harald Seidl

    Inventor： Ronald Kakoschke ,  Harald Seidl

    IPC: G11C11/00

    CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4966

    Abstract: One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.

    Abstract translation: 一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述衬底上的栅极堆叠，所述栅极堆叠包括设置在电荷存储层上的控制栅极; 以及设置在所述衬底上并且从所述栅极堆叠横向设置的间隔物选择栅极，所述选择栅极包括碳同素异形体。

    METHOD FOR PRODUCING AN INTEGRATED FIELD-EFFECT TRANSISTOR
    5.
    发明申请
    METHOD FOR PRODUCING AN INTEGRATED FIELD-EFFECT TRANSISTOR 有权
    用于生成集成场效应晶体管的方法

    公开(公告)号：US20100317162A1

    公开(公告)日：2010-12-16

    申请号：US12848576

    申请日：2010-08-02

    Applicant: Ronald Kakoschke

    Inventor： Ronald Kakoschke

    IPC: H01L21/336

    CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7855 ,  H01L29/78612

    Abstract: A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.

    Abstract translation: 提供了一种用于制造场效应晶体管的方法。 该方法包括形成衬底区域，在衬底区域形成两个端子区域，一个端子区域是源极区域，另一个端子区域是漏极区域，形成两个电绝缘绝缘层，它们布置在 并且与控制区域相邻，形成导电连接区域，该导电连接区域将导电连接区域和基板区域导电地连接到包含金属 - 半导体化合物的导电连接区域，在形成之后通过化学机械抛光来平整表面 控制区域，在抛光之后蚀刻回控制区域，并且在蚀刻后区域，基板区域和端子区域上进行用于形成金属 - 半导体化合物的自对准方法。

    VERTICAL FIELD-EFFECT TRANSISTOR
    7.
    发明申请
    VERTICAL FIELD-EFFECT TRANSISTOR 有权
    垂直场效应晶体管

    公开(公告)号：US20100142266A1

    公开(公告)日：2010-06-10

    申请号：US12704287

    申请日：2010-02-11

    Applicant: Ronald Kakoschke ,  Helmut Tews

    Inventor： Ronald Kakoschke ,  Helmut Tews

    IPC: G11C16/04 ,  H01L21/336 ,  G11C11/34

    CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/66666 ,  H01L29/7827

    Abstract: A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

    Abstract translation: 一种方法产生具有半导体层的垂直场效应晶体管，其中掺杂沟道区沿着凹陷布置。 “埋入”端子区域导通至半导体层的表面。 场效应晶体管还具有靠近凹陷的开口的掺杂端子区域以及远离开口的掺杂端子区域，布置在凹陷中的控制区域以及控制区域和沟道区域之间的电绝缘区域 。 远离开口的端子区域引出至包含开口的表面，或者导电地连接到通向该表面的导电连接。 控制区域仅布置在一个凹部中。 场效应晶体管是位于存储单元阵列的字线或位线处的驱动晶体管。

    BIT LINE STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF
    8.
    发明申请
    BIT LINE STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF 有权
    位线结构及其生产方法

    公开(公告)号：US20100129972A1

    公开(公告)日：2010-05-27

    申请号：US12695277

    申请日：2010-01-28

    Applicant: Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    Inventor： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    IPC: H01L21/762 ,  H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11521

    Abstract: A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

    Abstract translation: 为半导体元件或电路布置提供了位线结构和相关联的制造方法。 位线结构包含表面位线和掩埋位线。 掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。 通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。

    MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
    10.
    发明申请
    MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF 有权
    存储器电路布置及其生产方法

    公开(公告)号：US20090052219A1

    公开(公告)日：2009-02-26

    申请号：US12258728

    申请日：2008-10-27

    Applicant: Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schwelzer ,  Dominik Wegertseder

    Inventor： Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schwelzer ,  Dominik Wegertseder

    IPC: G11C5/02 ,  G11C5/06 ,  H01L21/00

    CPC classification number: G11C5/025 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

    Abstract translation: 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。

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