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公开(公告)号：US5812006A
公开(公告)日：1998-09-22
申请号：US739375
申请日：1996-10-29
申请人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
发明人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
IPC分类号： H03K17/06 , H03K17/082 , H03K5/08
CPC分类号： H03K17/063 , H03K17/0822
摘要： An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.
摘要翻译： 优化的功率输出钳位结构包括具有第一击穿电压的功率输出晶体管和具有耦合到功率输出晶体管的第二击穿电压的击穿结构。 第二击穿电压小于第一击穿电压，并且遵循所有温度和半导体工艺变化的第一击穿电压。 该特征允许降低击穿电压保护带并增加输出结构的可靠性。 还公开了一种保护电路免受感应回扫的方法。 该方法包括以下步骤：利用驱动电路驱动感性负载，关闭感性负载，以及钳位感应电压，电压幅度保护驱动电路不受所有温度和处理变化的影响。
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2.发明授权Method for current ballasting and busing over active device area using a multi-level conductor process 失效使用多层导体工艺在有源器件区域上进行电流镇流和放电的方法
公开(公告)号：US5801091A
公开(公告)日：1998-09-01
申请号：US903970
申请日：1997-07-31
申请人： Taylor R. Efland , Satwinder Malhi , Michael C. Smayling , Joseph A. Devore , Ross E. Teggatz , Alec J. Morton
发明人： Taylor R. Efland , Satwinder Malhi , Michael C. Smayling , Joseph A. Devore , Ross E. Teggatz , Alec J. Morton
IPC分类号： H01L23/482 , H01L23/528 , H01L29/417 , H01L29/78 , H01L21/44
CPC分类号： H01L23/5286 , H01L23/4824 , H01L29/41725 , H01L29/41758 , H01L29/7816 , H01L29/7835 , H01L2924/0002
摘要： The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.
摘要翻译： 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。
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3.发明授权Device having current ballasting and busing over active area using a multi-level conductor process 失效使用多层导体工艺在有源区域上进行电流镇流和放电的装置
公开(公告)号：US5665991A
公开(公告)日：1997-09-09
申请号：US456238
申请日：1995-05-31
申请人： Taylor R. Efland , Satwinder Malhi , Michael C. Smayling , Joseph A. Devore , Ross E. Teggatz , Alec J. Morton
发明人： Taylor R. Efland , Satwinder Malhi , Michael C. Smayling , Joseph A. Devore , Ross E. Teggatz , Alec J. Morton
IPC分类号： H01L23/482 , H01L23/528 , H01L29/417 , H01L29/78 , H01L23/522
CPC分类号： H01L23/5286 , H01L23/4824 , H01L29/41725 , H01L29/41758 , H01L29/7816 , H01L29/7835 , H01L2924/0002
摘要： The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.
摘要翻译： 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。
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4.发明授权Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5579193A
公开(公告)日：1996-11-26
申请号：US486926
申请日：1995-06-07
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, sensing circuitry 30 to sense a predetermined trigger current, and limitation circuitry 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，检测电路30以感测预定的触发电流，以及限制电路20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。
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5.发明授权Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5541799A
公开(公告)日：1996-07-30
申请号：US265609
申请日：1994-06-24
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，感测预定触发电流的装置30和装置20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。
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公开(公告)号：US06373094B1
公开(公告)日：2002-04-16
申请号：US09908024
申请日：2001-07-18
IPC分类号： H01L29788
摘要： An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20). The diffusion region (24 or 26) provides a source of charge for placement on the floating gate layer (22) when programming the EEPROM cell (10).
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公开(公告)号：US5675241A
公开(公告)日：1997-10-07
申请号：US672125
申请日：1996-06-27
CPC分类号： G05F3/247
摘要： A circuit and method for providing a low drop out voltage regulator. A source follower circuit is provided having a transistor (MD1) with an output terminal for driving a load at its source terminal and a voltage supply coupled to the drain terminal. At least one diode (D1) is coupled between the gate terminal and a ground reference to provide a predetermined voltage at the gate of the transistor (MD1). A voltage multiplier circuit is provided having an input (IN) for receiving an oscillating input voltage and a charge storage device (39) coupled between the oscillating input and a voltage reference (Vref), and being further coupled in series with the voltage reference and then to the gate terminal of the transistor (MD1). The oscillating input voltage is used to charge the charge storage device (39) to a voltage approximately equal to the voltage reference. When the supply voltage falls below the normal level, the series combination of the voltage reference and the charge storage device provides a multiplied voltage at the gate of the transistor, for example a voltage of twice the reference voltage. This high gate voltage keeps the output at the source of the transistor at a high voltage that is approximately equal to the supply voltage, such that the circuit provides a low drop out voltage under low supply voltage conditions.
摘要翻译： 一种用于提供低压降稳压器的电路和方法。 源极跟随器电路具有晶体管（MD1），其具有用于驱动其源极端子处的负载的输出端子和耦合到漏极端子的电压源。 至少一个二极管（D1）耦合在栅极端子和接地基准之间，以在晶体管（MD1）的栅极处提供预定的电压。 提供了具有用于接收振荡输入电压的输入（IN）和耦合在振荡输入和电压参考（Vref）之间的电荷存储装置（39）的电压倍增器电路，并进一步与电压基准串联耦合， 然后到晶体管（MD1）的栅极端子。 振荡输入电压用于将电荷存储装置（39）充电至大致等于电压基准的电压。 当电源电压低于正常电平时，电压基准和电荷存储装置的串联组合在晶体管的栅极处提供倍增电压，例如两倍于参考电压的电压。 该高栅极电压将晶体管源极处的输出保持在大致等于电源电压的高电压，使得该电路在低电源电压条件下提供低压降电压。
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公开(公告)号：US6111737A
公开(公告)日：2000-08-29
申请号：US267490
申请日：1999-03-11
CPC分类号： H01L27/0251
摘要： An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.
摘要翻译： 内部电路保护方案，当外部稳压器电压引脚短路到较高电压时，保护IC内部电路。 该电路通过钳位接收到的电压来防止损坏内部电压轨上的片上电路，从而消除了损坏管芯电路的可能性。 即使电压差大，电路也能提供保护，但在正常工作状态下，内部轨道与外部调节电压之间的差异仍然很小。
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公开(公告)号：US5710515A
公开(公告)日：1998-01-20
申请号：US480063
申请日：1995-06-07
IPC分类号： G01K7/01 , G01R31/28 , G01R31/30 , G01R31/3167 , H01L23/34 , G01R31/02 , G01R31/00 , G08B21/00
CPC分类号： H01L23/34 , G01K7/01 , G01R31/30 , G01R31/3167 , H01L2924/0002
摘要： A testable temperature warning circuit (120) in an integrated circuit substrate (124) provides a warning if the substrate temperature exceeds a critical temperature. A programming circuit (140) controls a selection, circuit (128) to establish a programmably selectable temperature at either the critical temperature or a second predetermined temperature lower than the critical temperature to enable the warning circuit operation to be tested at a temperature lower than the critical temperature. In one embodiment, the selection circuit 128 comprises a current source that produces a voltage drop across the resistor 121 and base-emitter of the transistor 122 produces a substrate temperature indicating current of magnitude related to the temperature of the substrate. The substrate temperature indicating current at the second temperature is extrapolatingly related to the substrate temperature indicating current at the critical temperature. A method is also presented for testing a temperature warning circuit fabricated in an integrated circuit substrate.
摘要翻译： 如果衬底温度超过临界温度，则集成电路衬底（124）中的可测温度警告电路（120）提供警告。 编程电路（140）控制选择电路（128）在临界温度或低于临界温度的第二预定温度下建立可编程选择的温度，以使报警电路操作能够在低于 临界温度。 在一个实施例中，选择电路128包括在电阻器121上产生电压降的电流源，并且晶体管122的基极 - 发射极产生指示与衬底温度相关的电流幅度的衬底温度。 指示在第二温度下的电流的衬底温度与指示临界温度下的电流的衬底温度外推相关。 还提出了一种用于测试在集成电路基板中制造的温度警告电路的方法。
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公开(公告)号：US06407626B1
公开(公告)日：2002-06-18
申请号：US09715759
申请日：2000-11-17
IPC分类号： H03K500
CPC分类号： H03K5/1252 , H03K5/082
摘要： Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.
摘要翻译： 提供了使用单个比较器的对称滤波器。 除了分压器，电流调节器和比较器之外，本发明的滤波器还提供控制逻辑，其接通或断开上拉开关和/或下拉开关以便完全充电或完全放电电容器。 因此，一方面，本发明是用于对称滤波器的控制逻辑。 此外，提供定时逻辑以提供更严格的对称滤波器性能。
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