公开(公告)号：US08462580B2

公开(公告)日：2013-06-11

申请号：US12948375

申请日：2010-11-17

申请人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

发明人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C7/22 ,  G11C11/36 ,  G11C11/34

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72

摘要： A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.

摘要翻译： 存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。 存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。 存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到 相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

公开(公告)号：US08576651B2

公开(公告)日：2013-11-05

申请号：US13354796

申请日：2012-01-20

申请人： Roy E. Scheuerlein ,  George Samachisa

发明人： Roy E. Scheuerlein ,  George Samachisa

IPC分类号： G11C7/04 ,  G11C5/14

CPC分类号： G11C11/5642 ,  G11C5/02 ,  G11C5/063 ,  G11C5/14 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2213/77

摘要： Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

公开(公告)号：US20130188431A1

公开(公告)日：2013-07-25

申请号：US13354796

申请日：2012-01-20

申请人： Roy E. Scheuerlein ,  George Samachisa

发明人： Roy E. Scheuerlein ,  George Samachisa

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C5/02 ,  G11C5/063 ,  G11C5/14 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2213/77

摘要： Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

摘要翻译： 描述了用于操作包括基于与半导体存储器阵列相关联的一个或多个阵列条件动态调整控制线电压（例如，未选择的字线或未选择的位线电压）的半导体存储器阵列的方法。 一个或多个阵列条件可以包括与半导体存储器阵列相关联的温度或与半导体存储器阵列相关联的特定数量的写周期。 在一些实施例中，基于一个或多个阵列条件产生中间电压并施加到半导体存储器阵列的未选字线和未选位线。 可以产生一个或多个中间电压，使得共享所选字线的未选择的存储单元之间的第一电压差与基于一个或多个阵列条件共享所选位线的其他未选择存储单元之间的第二电压差不同。

公开(公告)号：US20120120710A1

公开(公告)日：2012-05-17

申请号：US12948375

申请日：2010-11-17

申请人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

发明人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72

摘要： A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.

摘要翻译： 存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。 存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。 存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到 相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

公开(公告)号：US20120120711A1

公开(公告)日：2012-05-17

申请号：US12948388

申请日：2010-11-17

申请人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

发明人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

IPC分类号： G11C11/21 ,  G11C7/12

CPC分类号： G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092

摘要： A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.

公开(公告)号：US08355271B2

公开(公告)日：2013-01-15

申请号：US12948388

申请日：2010-11-17

申请人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

发明人： Peter Rabkin ,  George Samachisa ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092

摘要： A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.

摘要翻译： 存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。 存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。 存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到 相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

公开(公告)号：US08625322B2

公开(公告)日：2014-01-07

申请号：US13323766

申请日：2011-12-12

申请人： George Samachisa ,  Johann Alsmeier

发明人： George Samachisa ,  Johann Alsmeier

IPC分类号： G11C5/02

CPC分类号： H01L27/11551 ,  G11C5/025 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  H01L21/306 ,  H01L21/76224 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1616

摘要： A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size.

摘要翻译： 在位于半导体衬底上方不同距离的多个平面层上形成三维阵列读/写（R / W）存储元件。 优选以低电流和高电阻状态操作R / W元件。 这些电阻状态的电阻也取决于R / W元件的尺寸，并且由工艺技术预先确定。 与R / W元件串联的片状电极及其形成方法提供了另一个自由度来调节R / W存储元件的电阻。 调整片状电极的厚度，以便在从字线到位线的电路中获得减小的截面接触。 这允许R / W存储元件具有大大增加的电阻，因此以大大减小的电流工作。 片状电极形成的电池尺寸几乎没有增加。

公开(公告)号：US08580639B2

公开(公告)日：2013-11-12

申请号：US13875854

申请日：2013-05-02

申请人： Johann Alsmeier ,  George Samachisa

发明人： Johann Alsmeier ,  George Samachisa

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：US08575715B2

公开(公告)日：2013-11-05

申请号：US13571100

申请日：2012-08-09

申请人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

发明人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

IPC分类号： H01L29/66

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

摘要翻译： 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

公开(公告)号：US08547720B2

公开(公告)日：2013-10-01

申请号：US13151224

申请日：2011-06-01

申请人： George Samachisa ,  Luca Fasoli ,  Masaaki Higashitani ,  Roy Edwin Scheuerlein

发明人： George Samachisa ,  Luca Fasoli ,  Masaaki Higashitani ,  Roy Edwin Scheuerlein

IPC分类号： G11C5/02

CPC分类号： G11C16/10 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

摘要翻译： 存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。 存储元件响应于在其上施加的电压差而可逆地改变电导级。 三维阵列包括从基板到多层平面的两列立柱阵列。 第一组支柱线作为用于在每个平面上与字线阵列一起存取存储元件的局部位线。 第二组柱线连接到字线。 衬底上的金属线阵列可切换地连接到柱线以提供对第一和第二组柱线的接近，从而分别提供对三维阵列的位线和字线的访问。