公开(公告)号：US06723618B2

公开(公告)日：2004-04-20

申请号：US10206602

申请日：2002-07-26

申请人： Russell Meyer ,  Jeffrey W. Honeycutt ,  Stephen R. Porter

发明人： Russell Meyer ,  Jeffrey W. Honeycutt ,  Stephen R. Porter

IPC分类号： H01L218238

CPC分类号： H01L21/76205

摘要： Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench. Additional implementations are contemplated.

摘要翻译： 描述了现场隔离结构和形成场隔离结构的方法。 在一个实施方案中，该方法包括蚀刻单晶硅衬底内的沟槽。 沟槽具有侧壁和基底，底部包括单晶硅。 介电材料形成在沟槽的侧壁上。 外延单晶硅从沟槽的底部至少部分介电材料生长。 在外延单晶硅上形成绝缘层。 根据一个实施方案，本发明包括在包含单晶硅的衬底内形成的场隔离结构。 场隔离结构包括具有侧壁的沟槽。 电介质材料被容纳在沟槽内的侧壁上。 单晶硅被接纳在侧壁的电介质材料之间的沟槽内。 绝缘层被接纳在沟槽内的单晶硅上。 考虑附加实现。

公开(公告)号：US07245548B2

公开(公告)日：2007-07-17

申请号：US10900246

申请日：2004-07-27

申请人： Scott J. Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay S. Dixit ,  Scot M. Graham ,  Stephen R. Porter ,  Ethan A. Williford

发明人： Scott J. Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay S. Dixit ,  Scot M. Graham ,  Stephen R. Porter ,  Ethan A. Williford

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  G11C11/4085

摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

公开(公告)号：US06445610B1

公开(公告)日：2002-09-03

申请号：US09929611

申请日：2001-08-14

申请人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

发明人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

IPC分类号： G11C1124

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

摘要翻译： 在包含许多存储单元的数字线和读出放大器之间的DRAM器件中的隔离晶体管的栅极提供可变电压。 隔离晶体管的栅极被提供为在读取时间期间高于电源电压的电压，以确保数字线上的小差分电压被正确读取。 在感测时间提供较低的电压，使得隔离门在感测时间期间提供更高的电阻。 在恢复时间期间，隔离栅极电压再次升高到高于工作电压，以最小化隔离晶体管阈值电压Vt的影响。在另外的实施例中，仅在恢复时间期间提供较高电压，并且读取和检测电压在 更高和更低的电压。

公开(公告)号：US06438049B1

公开(公告)日：2002-08-20

申请号：US09256125

申请日：1999-02-24

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5004

摘要： A method and circuit for rapidly equilibrating paired digit lines of a memory array of a dynamic random access memory device is described. The equilibrate circuit includes a bias-circuit coupled to sense amplifier circuitry for adjusting the equilibrate voltage during testing. A method is described for testing memory cell margin by adjusting the equilibrate voltage until an error is detected. The bias circuit is described as a pull-up transistor coupled to a common mode of a cross-coupled n-sense amplifier.

摘要翻译： 描述了用于快速平衡动态随机存取存储器件的存储器阵列的成对数字行的方法和电路。 平衡电路包括耦合到读出放大器电路的偏置电路，用于在测试期间调节平衡电压。 描述了通过调整平衡电压直到检测到错误来测试存储单元余量的方法。 偏置电路被描述为耦合到交叉耦合n型放大器的共模的上拉晶体管。

公开(公告)号：US06396300B1

公开(公告)日：2002-05-28

申请号：US09467667

申请日：1999-12-17

申请人： Daniel R. Loughmiller ,  Stephen R. Porter

发明人： Daniel R. Loughmiller ,  Stephen R. Porter

IPC分类号： H03K1900

CPC分类号： H03K19/1732 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H03K19/1731

摘要： A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

公开(公告)号：US06355508B1

公开(公告)日：2002-03-12

申请号：US09290720

申请日：1999-04-12

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L21332

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

摘要翻译： 静电放电保护器件形成在衬底中，并且包含与掺杂剂浓度低于第一掺杂剂浓度的延伸漏极区相邻的第一掺杂剂浓度的漏区。 类似地，高掺杂源极区域邻接下掺杂源极延伸区域。 源极和漏极由氧化物区域横向界定并被绝缘层覆盖。 较低掺杂的区域通过在漏极的几乎平的底部表面电阻强制电流而不是弯曲的漏极延伸来防止静电放电事件期间的电荷拥挤。 此外，高度掺杂的掩埋层可以邻接渐变掺杂水平的区域。 通过调整分级区域和掩埋层的掺杂水平，预先选择衬底击穿电压。

公开(公告)号：US06219293B1

公开(公告)日：2001-04-17

申请号：US09388126

申请日：1999-09-01

申请人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

发明人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C11/4074

摘要： An internal voltage regulator for a synchronous random access memory “SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

摘要翻译： 用于同步随机存取存储器“SDRAM”的内部电压调节器）使用调节器电路来向不同于向SDRAM的阵列供电的调节器电路的电荷泵供电。 调节器为电荷泵提供输出电压，当外部电源电压提高到正常工作范围以上时，电荷泵保持恒定。 相比之下，向阵列供电的稳压电路随着电源电压增加超过正常工作范围而增加。 因此，电压调节器允许阵列以相对较高的调节输出电压进行压力测试，而不会对电荷泵施加过多的，潜在的破坏性的稳压输出电压。

公开(公告)号：US07426148B2

公开(公告)日：2008-09-16

申请号：US11294861

申请日：2005-12-05

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： G11C7/00

CPC分类号： G11C29/025 ,  G11C11/401 ,  G11C29/02

摘要： The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell associated with a first digit line to a first data value, programming a second memory cell associated with a second digit line to a second data value, the second data value being complementary with respect to the first data value, firing a first sense amplifier associated with the first digit line, firing a second sense amplifier associated with the second digit line after a time delay with respect to the act of firing the first sense amplifier associated with the first digit line, detecting a measured data value associated with the second digit line, and comparing the measured data value to the second data value to determine whether the first digit line is short circuited to the second digit line. The apparatus may comprise a first sense amplifier that is associated with a first digit line, a second sense amplifier that is associated with a second digit line, and a circuit that delays a firing operation of the second sense amplifier with respect to a firing operation of the first sense amplifier to allow detection of a short circuit between the first digit line and the second digit line.

摘要翻译： 所公开的实施例涉及用于识别集成电路装置中的短路的方法和装置。 该方法可以包括将与第一数字线相关联的第一存储器单元编程为第一数据值的动作，将与第二数字线相关联的第二存储器单元编程为第二数据值，第二数据值相对于 第一数据值，触发与第一数字线相关联的第一读出放大器，在相对于触发与第一数字线相关联的第一读出放大器的动作的时间延迟之后点火与第二数字线相关联的第二读出放大器， 检测与第二数字线相关联的测量数据值，以及将测量的数据值与第二数据值进行比较，以确定第一数字线是否短路到第二数字线。 该装置可以包括与第一数字线相关联的第一读出放大器，与第二数字线相关联的第二读出放大器，以及延迟相对于第二数字线的点火操作的第二读出放大器的点火操作的电路 第一读出放大器允许检测第一数字线和第二数字线之间的短路。

公开(公告)号：US07257043B2

公开(公告)日：2007-08-14

申请号：US11358234

申请日：2006-02-21

申请人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

发明人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/816 ,  G11C2207/002 ,  G11C2207/005 ,  Y10S257/906

摘要： A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

公开(公告)号：US06834019B2

公开(公告)日：2004-12-21

申请号：US10233325

申请日：2002-08-29

申请人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

发明人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

IPC分类号： G11C700

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/816 ,  G11C2207/002 ,  G11C2207/005 ,  Y10S257/906

摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。