Estimating wear of non-volatile, solid state memory
    1.
    发明授权
    Estimating wear of non-volatile, solid state memory 有权
    估计非挥发性固态记忆的磨损

    公开(公告)号:US08806106B2

    公开(公告)日:2014-08-12

    申请号:US12945496

    申请日:2010-11-12

    IPC分类号: G06F12/00

    摘要: Completion times of data storage operations targeted to a non-volatile, solid-state memory device are measured. Wear of the memory device is estimated using the measured completion times, and life cycle management operations are performed to affect subsequent wear of the memory device in accordance with the estimated wear. The life cycle management may include operations such as wear leveling, predicting an end of service life of the memory device, and removing worn blocks of the memory device from service.

    摘要翻译: 测量针对非易失性固态存储器件的数据存储操作的完成时间。 使用测量的完成时间估计存储器件的磨损,并且执行生命周期管理操作以根据估计的磨损影响存储器件的后续磨损。 生命周期管理可以包括诸如磨损均衡,预测存储器设备的使用寿命的结束以及从服务中去除存储器件的磨损块的操作。

    Sanitizing a non-volatile memory through charge accumulation
    3.
    发明授权
    Sanitizing a non-volatile memory through charge accumulation 失效
    通过电荷积累来消除非易失性记忆

    公开(公告)号:US08705291B2

    公开(公告)日:2014-04-22

    申请号:US13117913

    申请日:2011-05-27

    IPC分类号: G11C11/34 G11C16/04

    摘要: Method and apparatus for sanitizing a non-volatile memory, such as a flash memory array. In accordance with various embodiments, a memory cell is sanitized by using a write circuit to accumulate charge on a floating gate of the cell to a level such that application of a maximum available read sensing voltage to a control gate of the cell is insufficient to place the cell in a conductive state.

    摘要翻译: 用于消毒诸如闪存阵列的非易失性存储器的方法和装置。 根据各种实施例,通过使用写入电路将存储单元的浮动栅极上的电荷累积到使得将最大可用读取感测电压施加到单元的控制栅极不足以放置的水平来消毒存储器单元 电池处于导通状态。

    Sanitizing a Non-Volatile Memory Through Charge Accumulation
    4.
    发明申请
    Sanitizing a Non-Volatile Memory Through Charge Accumulation 失效
    通过电荷累积消除非易失性存储器

    公开(公告)号:US20120300554A1

    公开(公告)日:2012-11-29

    申请号:US13117913

    申请日:2011-05-27

    IPC分类号: G11C16/14 G11C16/04

    摘要: Method and apparatus for sanitizing a non-volatile memory, such as a flash memory array. In accordance with various embodiments, a memory cell is sanitized by using a write circuit to accumulate charge on a floating gate of the cell to a level such that application of a maximum available read sensing voltage to a control gate of the cell is insufficient to place the cell in a conductive state.

    摘要翻译: 用于消毒诸如闪存阵列的非易失性存储器的方法和装置。 根据各种实施例,通过使用写入电路将存储单元的浮动栅极上的电荷累积到使得将最大可用读取感测电压施加到单元的控制栅极不足以放置的水平来消毒存储器单元 电池处于导通状态。

    DYNAMIC FORMATION OF GARBAGE COLLECTION UNITS IN A MEMORY
    5.
    发明申请
    DYNAMIC FORMATION OF GARBAGE COLLECTION UNITS IN A MEMORY 审中-公开
    动态形成记忆中的收集单元

    公开(公告)号:US20140052897A1

    公开(公告)日:2014-02-20

    申请号:US13588716

    申请日:2012-08-17

    IPC分类号: G06F12/02 G06F12/00

    CPC分类号: G06F12/0246 G06F2212/7205

    摘要: Method and apparatus for managing data in a memory, such as but not limited to a flash memory. In accordance with some embodiments, a memory is provided with a plurality of addressable data storage blocks which are arranged into a first set of garbage collection units (GCUs). The blocks are rearranged into a different, second set of GCUs responsive to parametric performance of the blocks.

    摘要翻译: 用于管理存储器中的数据的方法和装置,例如但不限于闪速存储器。 根据一些实施例,存储器被提供有多个可寻址数据存储块,其被布置成第一组垃圾收集单元(GCU)。 响应于块的参数性能,块被重新排列成不同的第二组GCU。

    BACKGROUND DEDUPLICATION OF DATA SETS IN A MEMORY
    6.
    发明申请
    BACKGROUND DEDUPLICATION OF DATA SETS IN A MEMORY 有权
    数据集在存储器中的背景化

    公开(公告)号:US20130326115A1

    公开(公告)日:2013-12-05

    申请号:US13485455

    申请日:2012-05-31

    IPC分类号: G06F12/02

    摘要: Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored.

    摘要翻译: 存储器中的数据管理的装置和方法,例如但不限于闪存阵列。 根据一些实施例,存储器中的多个数据集被识别为在存储器中具有公共数据内容和不同的物理地址。 所选择的一个数据集被标记为有效数据,并且响应于与分别存储数据集的物理地址相关联的至少一个可变参数的评估,将剩余的数据集标记为陈旧的数据。

    Parametric Tracking to Manage Read Disturbed Data
    7.
    发明申请
    Parametric Tracking to Manage Read Disturbed Data 有权
    参数跟踪来管理读取干扰数据

    公开(公告)号:US20130258770A1

    公开(公告)日:2013-10-03

    申请号:US13438446

    申请日:2012-04-03

    IPC分类号: G11C16/26

    摘要: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, data are stored in a first location in a memory, and read from the first location a selected number of times. At least one parameter associated with the first location is measured after the data are read the selected number of times. The data are thereafter migrated to a second location in the memory responsive to the measured parameter indicating a presence of read disturbance in the data in the first location.

    摘要翻译: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据各种实施例,将数据存储在存储器中的第一位置,并从第一位置读取选定次数。 在数据读取所选择的次数之后,测量与第一位置相关联的至少一个参数。 此后,数据将根据测量的参数迁移到存储器中的第二位置,该参数指示在第一位置的数据中存在读取干扰。

    Allocating memory usage based on quality metrics
    8.
    发明授权
    Allocating memory usage based on quality metrics 有权
    根据质量指标分配内存使用情况

    公开(公告)号:US09058281B2

    公开(公告)日:2015-06-16

    申请号:US13486761

    申请日:2012-06-01

    IPC分类号: G06F12/00 G06F12/08

    摘要: A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations.

    摘要翻译: 分层存储器系统包括用于主存储器和次存储器的存储器控​​制器,其中辅存储器用作主存储器的高速缓存。 存储器控制器被配置为使得存储在存储器系统的主存储器中的冗余数据被存储在辅助存储器的第一存储器位置中。 控制器使未存储在主存储器中的数据存储在辅助存储器的第二存储单元中。 第二存储器位置具有比第一存储器位置更低的误码率和更高的存取速度中的至少一个。

    Background deduplication of data sets in a memory
    9.
    发明授权
    Background deduplication of data sets in a memory 有权
    内存中数据集的背景重复数据删除

    公开(公告)号:US08930612B2

    公开(公告)日:2015-01-06

    申请号:US13485455

    申请日:2012-05-31

    IPC分类号: G06F12/02 G06F3/06

    摘要: Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored.

    摘要翻译: 存储器中的数据管理的装置和方法,例如但不限于闪存阵列。 根据一些实施例,存储器中的多个数据集被识别为在存储器中具有公共数据内容和不同的物理地址。 所选择的一个数据集被标记为有效数据,并且响应于与分别存储数据集的物理地址相关联的至少一个可变参数的评估,将剩余的数据集标记为陈旧的数据。

    ALLOCATING MEMORY USAGE BASED ON QUALITY METRICS
    10.
    发明申请
    ALLOCATING MEMORY USAGE BASED ON QUALITY METRICS 有权
    基于质量标准分配内存使用

    公开(公告)号:US20130326116A1

    公开(公告)日:2013-12-05

    申请号:US13486761

    申请日:2012-06-01

    IPC分类号: G06F12/02 G06F12/08

    摘要: A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations.

    摘要翻译: 分层存储器系统包括用于主存储器和次存储器的存储器控​​制器,其中辅存储器用作主存储器的高速缓存。 存储器控制器被配置为使得存储在存储器系统的主存储器中的冗余数据被存储在辅助存储器的第一存储器位置中。 控制器使未存储在主存储器中的数据存储在辅助存储器的第二存储单元中。 第二存储器位置具有比第一存储器位置更低的误码率和更高的存取速度中的至少一个。